The system clock for all 16-bit PIC® MCU and dsPIC® MCUs includes a frequency multiplier branch built around a PLL (Phase-Locked Loop). Depending on the device variant, the following PLL types are implemented:
- 4x PLL (32MHz) (PIC24F GA, GC, KA, KL, KM)
- 24x PLL (96MHz) (PIC24F GB, DA)
- 80 MHz PLL (dsPIC33F/PIC24H)
- 140 MHz PLL (dsPIC33E/PIC24E)
The System PLL can use the Fast RC (FRC) or Primary (POSC) Oscillator as the input. The input is indirectly determined by the System Clock setting (FNOSC bits).
For some of these blocks, certain PLL parameters may be set at build-time via configuration bits, as well as at run-time via SFR register modification.