Programming the Peripheral Trigger Generator

# Establishing Step Command Timing

When setting up the clock controlling the execution speed of the Peripheral Trigger Generator (PTG) Step Commands three parameters need to be considered:

1. The signal used as the base clock source for the PTG Module
2. The number of clock periods needed for each Step Command cycle (prescaler).
3. Whether or not the sequence will need to extend the clock cycle (step delay timer).

## Clock Source and Prescaler

The PTG Control Register (PTGCON) controls the clock source and the prescale value for the PTG module. There are six signals which can be set as the PTG clock. Once the clock has been determined the application can divide the clock by a value between 1 and 32.

PTGCON: PTG Control Register

 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGCLK2 PTGCLK1 PTGCLK0 PTGDIV4 PTGDIV3 PTGDIV2 PTGDIV1 PTGDIV0 bit 15 bit 8

 R/W-0 R/W0 R/W0 R/W0 U-0 R/W-0 R/W-0 R/W-0 PTGPWD3 PTGPWD2 PTGPWD1 PTGWDT0 — PTGWDT2 PTGWDT1 PTGWDT0 bit 7 bit 0

bit 15-13

PTGCLK<2:0>: Select PTG Module Clock

111 = Reserved
110 = Reserved
101 = Clock source will be T3CLK
100 = Clock source will be T2CLK
011 = Clock source will be T1CLK
010 = Clock source will be ADC FRC clock
001 = Clock source will be Fosc
000 = Clock source will be Fp

bit 12-8

PTGDIV<4:0>: PTG Clock module Prescaler (Divider) value

11111 = Divide by 32
11110 = Divide by 31
*
*
*
0001 = Divide by 2
0000 = Divide by 1

## Delaying PTG Step cycle.

Using the PTG Step Delay Limit Regsiter (PTGSDLIM) causes the Step Commands lot execute at a slower rate than the period set by PTGCON. When enabled, PTGSDLIM acts as an second prescaler for the PTG Module; the PTG clock will be divided by the value of PTGSDLIM. The use of the step delay timer is optional as it can enabled or disabled at runtime by using the PTGCTRL Step Command.

• PTGCTRL with <OPTION> = 0b0010 (2) Disables the Step Delay
• PTGCTRL with <OPTION> = 0b0110 (6) Enables the Step Delay

Step commands are executed from the Peripheral Trigger Generator (PTG) Step queue. The Step queue is a set of 16-bit wide special function registers (SFRs). The number of entries in the queue varies depending upon which MCU is being used. The SFRs in the queue are PTGQUE0 through PTGQUEn (where n = ( # of Step commands/2 ) - 1). Two 8-bit wide Step Commands are loaded into each 16-bit wide Step queue SFR.

### Compiler Supplied #defines

The Step queue is loaded with a series of assignment statements. When <xc.h> is included in a project the MPLAB® XC16 compiler provides easy-to-read definitions for the individual queue entries (e.g., _STEP0, _STEP1, etc..). The compiler definitions ensure the proper placement of Step Commands.

### Application #defines

A common mechanism used in application programs is to #define the commands in such a way as to make the loading of the queue more readable. Using this mechanism the #define includes the numeric opcode left shifted by 4 bits. Combined with the numeric for the OPTION field, this mechanism allows you to easily see what has been loaded into the queue.

# Enabling and Starting the PTG

In order for the Peripheral Trigger Generator (PTG) to begin executing Step Commands two separate actions must be taken by the application:

1. The PTG must first be Enabled
2. Once enabled, the PTG will begin operating when it is Started

Enabling and Starting the PTG are accomplished by writing to the PTG Control and Status Register PTGCST.

PTGCST: PTG Status and Control Register

 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PTGEN — PTGSIDL PTGTOGL — PTGSWT PTGSSEN PTGVIS bit 15 bit 8

 R/W-0 R/W0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 PTGSTRT PTGWDT0 — — — — PTGITM1 PTGITM0 bit 7 bit 0

bit 15

PTGEN: Module Enable bit

1 = Enables the PTG module
0 = Disables the PTG module

bit 7

PTGSTRT: Start PTG Sequencer bit

1 = Start to sequentially execute Step commands
0 = Stop executing commands

### Notes to remember on Enabling and Starting the PTG

• At reset the PTG module is Disabled and Stopped.
• PTGCST is the only PTG Special Function Register (SFR) which can be written while the PTG Module is enabled. To modify any other PTG SFR you must first disable the PTG by clearing PTGEN.
• When PTGEN is set, the PTG Queue Pointer Register (PTGQPTR) is set to point to the first entry in the Step Queue. Starting and stopping PTG execution has no effect on PTGQPTR.

Initializing the PTG