Establishing Step Command Timing
When setting up the clock controlling the execution speed of the Peripheral Trigger Generator (PTG) Step Commands three parameters need to be considered:
- The signal used as the base clock source for the PTG Module
- The number of clock periods needed for each Step Command cycle (prescaler).
- Whether or not the sequence will need to extend the clock cycle (step delay timer).
Clock Source and Prescaler
The PTG Control Register (PTGCON) controls the clock source and the prescale value for the PTG module. There are six signals which can be set as the PTG clock. Once the clock has been determined the application can divide the clock by a value between 1 and 32.
PTGCON: PTG Control Register
|bit 15||bit 8|
|bit 7||bit 0|
PTGCLK<2:0>: Select PTG Module Clock
111 = Reserved
110 = Reserved
101 = Clock source will be T3CLK
100 = Clock source will be T2CLK
011 = Clock source will be T1CLK
010 = Clock source will be ADC FRC clock
001 = Clock source will be Fosc
000 = Clock source will be Fp
PTGDIV<4:0>: PTG Clock module Prescaler (Divider) value
11111 = Divide by 32
11110 = Divide by 31
0001 = Divide by 2
0000 = Divide by 1
Selecting the PTG clock and prescaler using the MPLAB® XC16 C Compiler
Delaying PTG Step cycle.
Using the PTG Step Delay Limit Regsiter (PTGSDLIM) causes the Step Commands lot execute at a slower rate than the period set by PTGCON. When enabled, PTGSDLIM acts as an second prescaler for the PTG Module; the PTG clock will be divided by the value of PTGSDLIM. The use of the step delay timer is optional as it can enabled or disabled at runtime by using the PTGCTRL Step Command.
- PTGCTRL with <OPTION> = 0b0010 (2) Disables the Step Delay
- PTGCTRL with <OPTION> = 0b0110 (6) Enables the Step Delay