ARM Cortex®-M0+ Pipeline

The ARM® Cortex®-M0+ core has a two stage pipeline (Cortex-M0, M3 and M4 have three stages). This two stage pipeline decreases the core response time and power consumption.

  • Stage 1: Fetch & Pre-decode
  • Stage 2: Main decode & Execute

When older Cortex-M cores (with a three stage pipe) execute a conditional branch, the next instructions are no longer valid. This means that the pipeline must be flushed everytime there is a branch. By moving to a two stage pipeline, access to Flash is minimized and power consumption is lowered. Flash memory power often contributes the majority of the power consumed in a microcontroller, so any reduction in Flash accesses has a very direct effect on the total power consumed.

© 2017 Microchip Technology, Inc.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.