Sigma-Delta ADC Compared to SAR ADC

This page helps you to understand the operation of the SAM C21 Sigma-Delta ADC module by comparing its operation to that of the Successive Approximation Register (SAR) Analog-to-Digital Conversion (ADC) method.

Successive Approximation Conversion Method

sar-adc-block-diagram.png


The SAR converter takes a sample of the analog input at the time the conversion is requested. The sample is compared to the output of a Digital-to-Analog Converter (DAC). The DAC is initialized with the MSB high and all other bits low, then the output of the comparator determines if the analog sample or the DAC is higher. If the analog sample is higher, the MSB is left high, if the DAC is higher, then the MSB is set low. The next lower bit is then set and the comparator output again determines whether that bit remains set or is cleared. After n comparisons, an n-bit result is available that represents the numeric equivalent of the analog input. Because each comparison is done at a different point in time, it is very important that the analog sample does not change over that time, or the resulting number would be invalid. This is the purpose of the Sample and Hold circuit, which is essentially a switch and a capacitor to store the analog voltage. The switch is opened during the conversion, so the capacitor holds the analog value present when the conversion is started.

Sigma-Delta Conversion Method

The Sigma-Delta ADC operates in a completely different manner. Instead of taking discrete samples of the analog signal, the input is converted into a continuous process. The difference between the input and a 1-bit DAC is fed into an integrator. The output of the integrator is compared against a voltage reference, and the result of that comparison sets the next value of the DAC:

sdadc-block-diagram-modulator.png


Why use a 1-bit DAC? First, it is really simple and is basically just a switch to Vref or -Vref. Another reason is a shortcoming in the multi-bit DACs used in SAR converters. These DACs are typically built up with a resistor ladder and since there are different components used for each bit, there is a tolerance on each bit, so each bit may be a slightly different size which affects the precision of the result. The 1-bit DAC in the Sigma-Delta converter ensures that each bit is exactly the same size. The weight of each bit towards the final result is determined by the amount of time that bit is applied to the integrator. In a SAR converter, the clock applied to the module only affects the amount of time the conversion takes – in the Sigma-Delta converter, the sample clock determines the bit size. There is no Sample and Hold in the Sigma-Delta converter because of the continuous operation, but it is still important that the input does not change faster than the converter can process the changes, so the sample rate must be much higher than any frequency present in the analog input signal.

The output of the Sigma-Delta modulator is a stream of single bits and the ratio of ones to zeroes in that stream are based on the analog input value. To get a multi-bit result from the module, the bitstream is run through a digital filter. The output of the filter is then decimated, which results in fewer samples with more bits. The decimation is controlled by the Over-Sampling Ratio (OSR), which in the SAM C21 SDADC module is a power of 2 between 64 and 1024:

sdadc-block-diagram-decimator.png

Why is the decimation filter input 2 bits wide? The SAM C21 Sigma-Delta ADC module is differential, so the output may be positive or negative. Because of this, the bitstream out of the Sigma-Delta modulator is actually 2 bits per sample, because a sign bit is needed.

Switching Input Channels

Because the bitstream out of the Sigma-Delta converter is continuous instead of a discrete time sample like the SAR converter, you can’t just switch a multiplexer to a particular channel and make a one-time sample like you can with a SAR. When you start a conversion, you must run enough samples through for the integrator to settle to its ultimate value (22 samples through the Sigma-Delta modulator in the SAM C21), then you must discard several samples out of the decimation filter while it settles to its value (three samples from the output after the OSR on the SAM C21).

Correcting the Output Value

While the bit sizes are all uniform in the Sigma-Delta converter, there are a couple of sources of error to be concerned about. First is an Offset error, due to offset in the Differentiator and the Comparator, a zero input may give a non-zero output. Second is a Gain error – because the bit size and sample time may not exactly equal a full-scale output. To fix these errors, you must sample a zero input and a full-scale input, and apply correction factors to the output value to get the correct output.

In the SAM C21, the corrections are applied automatically in the hardware. An offset correction is added to the result, and then that value is multiplied by the gain correction. The output register is 24-bits, so the corrections can be applied to the 16-bit maximum resolution without having to worry about overflow in the correction process. The software must take samples at zero and full-scale inputs to determine the appropriate correction factors, and then set these correction factors into the appropriate registers in the Sigma-Delta ADC module.

 Learn More

 
Sigma-Delta ADC Overview
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Sigma-Delta ADC Configuration
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Sigma-Delta ADC Example Project
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