SAM D21 Direct Memory Access Controller (DMAC) Overview

Module Overview

SAM devices with Direct Memory Access Controller (DMAC) enables high data transfer rates with minimum CPU intervention and frees up CPU time. With access to all peripherals, the DMAC can handle an automatic transfer of data to/from modules. It supports static and incremental addressing for both source and destination.

The DMAC, when used with Event System or peripheral triggers, provides a considerable advantage by reducing the power consumption and performing data transfer in the background. For example, if the Analog to Digital Converter (ADC) is configured to generate an event, it can trigger the DMAC to transfer the data into another peripheral or SRAM. The CPU can remain asleep during this time to reduce the power consumption.

Device DMA channel number
SAM D21/R21/C20/C21 12
SAM D09/D10/D11 6
SAM L21 16

The DMA channel operation can be suspended at any time by software, by events from the event system, or after selectable descriptor execution. The operation can be resumed by software or by events from the event system. The DMAC driver for SAM supports four types of transfers such as peripheral to peripheral, peripheral to memory, memory to peripheral, and memory to memory.

The basic transfer unit is a beat, which is defined as a single bus access. There can be multiple beats in a single block transfer and multiple block transfers in a DMA transaction. DMA transfer is based on descriptors, which holds transfer properties such as the source and destination addresses, transfer counter, and other additional transfer control information. The descriptors can be static or linked. When static, a single block transfer is performed. When linked, a number of transfer descriptors can be used to enable multiple block transfers within a single DMA transaction.

The implementation of the DMA driver is based on the idea that the DMA channel is a finite resource of entities with the same abilities. A DMA channel resource can move a defined set of data from a source address to a destination address triggered by a transfer trigger. On the SAM devices, there are 12 DMA resources available for allocation. Each of these DMA resources can trigger interrupt callback routines and peripheral events. The other main features are:

  • Selectable transfer trigger source
  • Software
  • Event System
  • Peripheral
  • Event input and output is supported for the four lower channels
  • Four-level channel priority
  • Optional interrupt generation on transfer complete, channel error, or channel suspend
  • Supports multi-buffer or circular buffer mode by linking multiple descriptors
  • Beat size configurable as 8-bit, 16-bit, or 32-bit.

A simplified block diagram of the DMA Resource is shown in the figure below.


Driver Feature Macro Definition

Driver Feature Macro Supported devices

The specific features are only available in the driver when the selected device supports those features.

Terminology Used in DMAC Transfers

Name Description
Beat A single bus access by the DMAC. Configurable as 8-bit, 16-bit, or 32-bit.
Burst A transfer of n-beats (n = 1, 4, 8, 16). For the DMAC module in SAM, the burst size is one beat. Arbitration takes place each time a burst transfer is completed.
Block transfer A single block transfer is a configurable number of (1 to 64 k) beat transfers.

DMA Channels

The DMAC in each device consists of several DMA channels, which, along with the transfer descriptors, defines the data transfer properties.

  • The transfer control descriptor defines the source and destination addresses. The source and destination address increment settings, the block transfer count, and event output condition selection.
  • Dedicated channel registers control the peripheral trigger source, trigger mode settings, event input actions, and channel priority level settings.

With a successful DMA resource allocation, a dedicated DMA channel is assigned. The channel will be occupied until the DMA resource is freed. A DMA resource handle is used to identify the specific DMA resource. When there are multiple channels with active requests, the arbiter prioritizes the channels requesting access to the bus.

DMA Triggers

DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A transfer request can be triggered by a software, a peripheral, or an event. There are dedicated source trigger selections for each DMA channel usage.

DMA Transfer Descriptor

The transfer descriptor resides in the SRAM and defines these channel properties.
Field name Field width
Descriptor Next Address 32 bits
Destination Address 32 bits
Source Address 32 bits
Block Transfer Counter 16 bits
Block Transfer Control 16 bits

Before starting a transfer, at least one descriptor should be configured. After a successful allocation of a DMA channel, the transfer descriptor can be added with a call to dma_add_descriptor(). If there is a transfer descriptor already allocated to the DMA resource, the descriptor will be linked to the next descriptor address.

DMA Interrupts/Events

Both an interrupt callback and a peripheral event can be triggered by the DMA transfer. Three types of callbacks are supported by the DMA driver: transfer complete, channel suspend, and transfer error. Each of these callback types can be registered and enabled for each channel independently through the DMA driver API.

The DMAC module can also generate events on a completed transfer. Event generation is enabled through the DMA channel, event channel configuration, and event user multiplexing is done through the events driver.

The DMAC can generate events in the following cases:

  • When a block transfer is complete
  • When each beat transfer within a block transfer is complete

 Learn More

Direct Memory Access Controller Configuration
Learn more >
Direct Memory Access Controller Example Project (GCC)
Learn more >
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