SAM D21 External Interrupt Controller (EIC) Overview

The External Interrupt Controller (EIC) allows up to 16 external pins (EXTINTx) to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling, or both edges, or on high or low levels.

Each external pin:

  • has a configurable filter to remove spikes,
  • can be configured to be asynchronous (in order to wake up the device from sleep modes where all clocks have been disabled), and
  • can also generate an event.

A separate, non-maskable interrupt (NMI) is also supported. An NMI cannot, as the name suggests, be disabled in firmware and will take precedence over any in-progress interrupt sources. NMIs can be used to implement critical device features, such as forced software reset, or other functionality where the action should be executed in preference to all other running code, with a minimum amount of latency.

A generic clock (GCLK_EIC) is required to clock the peripheral. This clock must be configured and enabled in the Generic Clock Controller before using the peripheral. This generic clock is asynchronous to the user interface clock (CLK_EIC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains.

EIC Block Diagram


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EIC Configuration
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EIC Example Project
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