Cortex®-M0+ High Speed Bus

The Arm® Cortex®-M0+ system bus (AHB) is a 32-bit multi-master/multi-slave bus matrix capable of performing multiple concurrent transactions per instruction cycle. Combined with the CPU's ability to directly access the I/O ports through IOBUS, the AHB enables M0+ instructions to execute instructions without performance hindering wait-states.

The AHB is Microchip's implementation of Arm Advanced Microcontroller Bus Architecture (AMBA®). AMBA is an open standard on-chip specification for interconnecting function blocks in microcontrollers and system on chip (SoC) devices. Since its initial release in 1996, AMBA has gone through several modifications and revisions. Cortex-M0+ MCU High-speed buses use the AMBA-3 AHB-lite specification.

cm0plus-ahb-general.png

AHB Features

  • An Inherent architectural feature of Cortex-M0+ MCUs, the AHB requires no user configuration.
  • Provides high-performance instruction execution.
  • Enables the CPU to seamlessly access slower peripherals by interfacing with the AHB peripheral bus (AHB-APB) bridges.

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AHB-APB Bridge
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DMA Controller
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Device Service Unit
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M0+ CPU
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