SAM D21 Inter-IC Sound Controller (I²S™) Overview

The I²S™ provides a bi-directional, synchronous, digital audio link with external audio devices through these signal pins:

  • Serial Data (SDm)
  • Frame Sync (FSn)
  • Serial Clock (SCKn)
  • Master Clock (MCKn)

The I²S consists of two clock units and two Serializers, which can be separately configured and enabled to provide the following functionalities:

  • communicate to audio CODECs as master or slave, or provide clock and frame sync signals as a controller
  • communicate to Digital to Analog Converter (DAC) or Analog to Digital Converter (ADC) through dedicated I²S serial interface
  • communicate to multi-slot or multiple stereo DACs or ADCs, via Time Division Multiplexed (TDM) format
  • read mono or stereo microelectromechanical systems (MEMS) microphones, using the Pulse Density Modulation (PDM) interface.

The I²S supports compact stereo data word where left channel data bits are in the lower half and right channel data bits are in the upper half. It reduces the number of data words for stereo audio data and the direct memory access (DMA) bandwidth.

In master mode, the frame is configured by a number of slots and slot size. This allows a range covering 16 fs to 1024 fs MCK to provide an oversampling clock to an external audio CODEC or digital signal processor (DSP). A block diagram of the I²S is shown in the figure below.

I2S-Block-Diagram.PNG

This driver for I²S module provides an interface to:

  • initialize and control I²S module
  • configure and control the I²S Clock Unit and Serializer
  • transmit/receive data through I²S Serializer.

Clocks

To use the I²S module, the I²S bus interface clock (clk_i2s) must be enabled via Power Manager.

For each I²S clock unit, a generic clock (gclk_i2s_n) is connected. When I²S works in master mode the generic clock is used, it should be prepared before the clock unit is used. In master mode, the input generic clock will be used as a master clock (MCK) for SCKn and FSn generation, in addition, the MCK could be divided and output to an I²S MCKn pin, as an oversampling clock to the external audio device.

The I²S Serializer uses clock and control signal from the clock unit to handle the transfer. Selecting different clock units with different configurations allow the I²S to work as a master or a slave, to work on non-related clocks.

Audio Frame Generation

Audio sample data for all channels are sent in frames, one frame can consist of one to eight slots where each slot can be configured to be 8-bit, 16-bit, 24-bit, or 32-bit. The audio frame sync clock is generated by the I²S clock unit in the master/controller mode. The frame rate (or frame sync frequency) is calculated as follows:

FS = SCK / number_of_slots / number_of_bits_in_slot

The serial clock (SCK) source is either an external source (slave mode) or generated by the I2S clock unit (controller or master mode) using the MCK as the source.

SCK = MCK / sck_div

SCK generation division value is 'MCKDIV' in the register. MCK is either an external source or generated using the GCLK input from a generic clock generator.

Master, Controller, and Slave Modes

The I²S module has three modes: master, controller, and slave.

Master

In master mode, the module controls the data flow on the I²S bus and can be responsible for clock generation. The Serializers are enabled and transmits/receives data. On a bus, with only master and slave, the SCK and FS clock signal is outputted on the SCK and FS pin on the master module. MCK can optionally be outputted on the MCK pin if there is a controller module on the bus. The SCK, FS, and, optionally, the MCK clock is sourced from the same pins. Serial data will be transceived on the SD pin in both scenarios.

Controller

In controller mode, the module generates the clock signals, but the Serializers are disabled and no data is transmitted/received by the module in this mode. The clock signals are outputted on the SCK, FS and optionally the MCK pin.

Slave

In slave mode, the module uses the SCK and FS clock source from the master or the controller which is received on the SCK and FS pin. The MCK can optionally be sourced externally on the MCK pin. The Serializers are enabled and will transceive data on the SD pin. All data flow is controlled by the master.

Switch Modes

The mode switching between master, controller, and slave is done by modifying the source mode of I²S pins. The source mode of I²S pins is selected by writing the corresponding bits in CLKCTRLn. Since source mode switching changes the direction of a pin, the mode must be changed when the I²S Clock Unit is stopped.

Data Stream Reception/Transmission

The I²S module supports several data stream formats:

  • I²S format
  • Time Division Multiplexed (TDM) format
  • Pulse Density Modulation (PDM) format (reception only)

Basically, the I²S module can send several words within each frame; it is more like a TDM format. By adjusting to the number of data words in a frame, the FS width, the FS to data bits delay, etc., the module is able to handle I²S compliant data stream. Also, the Serializer can receive PDM format data stream, which allows the I²S module receive 1 PDM data on each SCK edge.

I²S Stream Reception/Transmission

For a 2-channel I²S compliant data stream format the I²S module uses the FS line as word select (WS) signal and sends left channel data word on a low WS level and right channel data word on a high WS level as specified in the I²S standard. The supported word sizes are 8-, 16-, 18-, 20-, 24-, and 32- bit.

Thus for I²S stream, the following settings should be applied to the module:

  • Data starting delay after FS transition: one SCK period
  • FS width: half of the frame
  • Data bits adjust in a word: left-adjusted
  • Bit transmitting order: MSB first

An example of I²S application connections and waveforms is shown in the following image.

I2S-Example-Diagram.PNG

TDM Stream Reception/Transmission

In TDM format, the module sends several data words in each frame. For this data stream format, most of the configurations can be adjusted. Main Frame related settings are as follows:

  • Frame Sync (FS) options:
    • The active edge of the FS (or if FS is inverted before use)
    • The width of the FS
  • The delay between FS to the first data bit
  • Data alignment in slot
  • The number of slots and slot size can be adjusted.
  • The data word size is controlled by the Serializer, it can be chosen from 8-, 16-, 18-, 20-, 24-, and 32- bits.

The general TDM waveform generation is as follows:

TDM-Waveform-Generation.PNG

Data formatting and pin multiplexer (MUX) settings can also be used to set up the clock. The following figures are examples for different application use cases.

See figure below Codec Example Diagram for the Time Slot Application connection and waveform example.

Codec-Example-Diagram.PNG

See figure below Time Slot Example Diagram for the Codec Application connection and waveform example.

Time-Slot-Example-Diagram.PNG

PDM Reception

The I²S Serializer integrates the PDM reception feature, to use this feature, simply select 'PDM2' mode in the Serializer configuration. In PDM2 mode, it assumes two microphones are set up as input for the stereo stream. The left microphone bits will be stored in the lower half and right microphone bits in the upper half of the data word, like in compact stereo format.

See the "Time PDM2 Example Diagram" for a PDM Microphones application example, with both left and right channel microphones connected.

Time-PDM2-Example-Diagram.PNG

MONO and Compact Data

The I²S Serializer can accept some pre-defined data format and generate the data stream in a specified way.

When transmitting data, the Serializer can work in MONO format:

  • Transmit mode: Data written to the left channel is duplicated to the right output channel.
  • Receiver mode: Data received from the right channel is ignored and data received from the left channel is duplicated into the right channel.

Also, the I²S Serializer can support compact stereo data word. The data word size of the Serializer can be set to 16-bit compact or 8-bit compact. With these options, the I²S Serializer compacts the left channel data and right channel data together; the left channel data will take lower bytes and right channel data will take higher bytes.

Loop-back Mode

The I²S can be configured to loop back the transmitter to the receiver. In this mode, the Serializer's input is connected to another Serializer's output internally.

Sleep Modes

The I²S will continue to operate in any sleep mode where the selected source clocks are running.

 Learn More

 
I²S Configuration
Learn more >
 
I²S Example Project
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