Arm® Cortex®-M0+ Single Cycle IOBUS

Last modified by Microchip on 2023/11/09 09:01

The Arm® Cortex®-M0+ CPU's local bus (IOBUS) provides a direct connection between the CPU and the PORT. IOBUS transactions bypass the Advanced High-performance Bus (AHB) bus allowing I/O pins to be manipulated in a single instruction cycle. IOBUS transactions are not subject to any wait states induced by AHB bus arbitration.

AHB  bus matrix block diagram
The IOBUS is used when the CPU performs read or write from address 0x60000000. There are no user-supplied initialization or configuration settings needed to use the IOBUS. The default mode of the MPLAB® XC32 C/C++ Compiler is to use the IOBUS for all digital I/O.