SAM D21 Memory Architecture

The memory on a SAM D21 MCU is mapped into four sections:

  • Flash Memory
  • Flash Memory with Read-While-Write (RWW) capability
  • Internal RAM
  • Peripherals and I/O ports
memory-map.png

Flash Memory

The flash memory is non-volatile memory used to store executable instructions as well as some calibration data and default configuration settings. SAMD21 compilers will use most of the flash memory addresses to store instructions.

A predetermined range of the flash memory addresses is designated as auxiliary memory. Auxiliary memory contains factory-set calibration data as well as the NVM user Row. The NVM user Row establishes the default setting for the Watch Dog Timer, Brownout detector, and the flash RWW memory.

calibration.png

Some experienced PIC® MCU developers will see the similarities between an Arm® Cortex®-M0+ NWM user row and PIC configuration words.

Flash Memory with Read-While-Writing (RWW) capability:

The RWW is only available on some D21 MCUs. RWW is the portion of the flash array that can be set to emulate EEPROM. The amount of flash available for EEPROM emulation is established by the non-volatile memory controller NVMCTRL.

Internal High-Speed RAM

The internal high-speed RAM allows the CPU to read or write application data in a single instruction cycle. Please refer to the data sheet for the amount of memory on the device you are using.

Peripheral Bridges and I/O Ports

The peripheral's registers and the registers controlling the I/O pins are mapped to memory locations. The CPU accesses the peripherals and I/O pin registers by reading or writing to specific mapped memory addresses. Peripherals are accessed through one of three peripheral bridges. Direct access to the I/O pins is accomplished by accessing the IOBUS mapped addresses.

 Learn More

 
NVM Controller (NVMCTRL)
Learn more >
 
Configuring the NVM Controller
Learn more >
 
Peripheral Bridges
Learn more >
 
IOBUS
Learn more >
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