SAM L10/L11 32K Oscillators Controller

Last modified by Microchip on 2023/11/15 17:38
Contents

Overview

The 32 kHz Oscillators Controller (OSC32KCTRL) provides a user interface to the 32.768 kHz oscillators: XOSC32K and OSCULP32K.

The OSC32KCTRL sub-peripherals can be enabled, disabled, calibrated, and monitored through interface registers.

All sub-peripheral statuses are collected in the Status (STATUS) register. They can additionally trigger interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers.

Features

  • 32.768 kHz Crystal Oscillator (XOSC32K)
  • Programmable start-up time
  • Crystal or external input clock on XIN32 I/O
  • Clock failure detection with safe clock switch
  • Clock failure event output
  • 32.768 kHz Ultra-low Power Internal Oscillator (OSCULP32K)
    • Ultra-low power, always-on oscillator
    • Frequency fine-tuning
  • Calibration value loaded from Flash factory calibration at reset
  • 1.024 kHz clock outputs available

OSC32KCTRL Block Diagram

SAM L10 32K Oscillator Controller

The OSC32KCTRL will continue to operate in any Sleep mode where a 32 kHz oscillator is running as the source clock. The OSC32KCTRL interrupts can be used to wake up the device from Sleep modes. The OSC32KCTRL bus clock (CLK_OSC32KCTRL_APB) can be enabled and disabled in the Main Clock (MCLK) module.

The interrupt request lines are connected to the interrupt controller. Using the OSC32KCTRL interrupts requires the interrupt controller to be configured first.

The external 32.768 kHz crystal must be connected between the XIN32 and XOUT32 pins, along with any required load capacitors. For details on recommended oscillator characteristics and capacitor load, refer to the "Electrical Characteristics" section of the product datasheet.

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Principle of Operation

XOSC32K and OSCULP32K are configured via OSC32KCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled, or have their calibration values updated. The STATUS register gathers different status signals coming from the sub-peripherals of OSC32KCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from Standby mode, provided the corresponding interrupt is enabled.

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Code Example

​/***
 *** The Example has no copyright and can be used by anyone.
 *** The following example is based on Device File Package
 *** required to compile the macro definitions used.
 *** The Device File Package is available by downloading Atmel Studio 7.
 ***/
 
void configure_32K_clocks(void)
{
 
 /*** Enable XOSC32K 
  *** Enable XTAL drive
  *** Enable 1KHz output
  *** Enable 32KHz output
  *** Set a Start up time to 5 which represents around 4s start-up time.
  *** Enable GCLK2 with XOSC32K as clock source for TC0 (eventually) 
  ***/
 OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE|
                           OSC32KCTRL_XOSC32K_XTALEN|
                           OSC32KCTRL_XOSC32K_EN1K|
                           OSC32KCTRL_XOSC32K_EN32K|
                           OSC32KCTRL_XOSC32K_STARTUP(5);
 while(OSC32KCTRL->STATUS.bit.XOSC32KRDY==0);
 
 /*** Enable GCLK2 with XOSC32K as clock source for TC0 for ADC 1KHz Triggering ***/
 GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(1) | CURRENT_32KOSC |GCLK_GENCTRL_GENEN;
 /*** (write synchronized) ***/
 while((GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2));
 GCLK->PCHCTRL[GCLK_TC0].reg = (GCLK_PCHCTRL_CHEN|GCLK_PCHCTRL_GEN_GCLK2);
}

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