SAM L10/L11 External Interrupt Controller (EIC)

Overview

The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling, or both edges or on high or low levels. Each external pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous in order to wake up the device from Sleep modes where all clocks have been disabled. External pins can also generate an event. Each external pin can be defined as secured or non-secured, whereas secured pins can only be handled by secure accesses. A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts but is connected to the NMI request of the CPU, enabling it to interrupt any other Interrupt mode.

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Features

• Up to eight external pins (EXTINTx), plus one non-maskable pin (NMI)
• Dedicated, individually maskable interrupt for each pin
• Interrupt on rising, falling, or both edges
• Synchronous or asynchronous edge detection mode
• Interrupt pin debouncing
• Interrupt on high or low levels
• Asynchronous interrupts for Sleep modes without clocks
• Filtering of external pins
• Event generation from EXTINTx
• Selectable secured or non-secured attribution for each individual external pin (SAM L11)

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Block Diagram

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Principle of Operation

There are several interrupt request lines, at least one for the external interrupts (EXTINT) and one for Non-Maskable Interrupt (NMI). The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the interrupt controller to be configured first. The NMI interrupt request line is also connected to the interrupt controller but does not require the interrupt to be configured. The events are connected to the Event System. Using the events requires the Event System to be configured first.

The EIC detects edge or level conditions to generate interrupts to the CPU interrupt controller or events to the Event System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by GCLK_EIC or by CLK_ULP32K.

The EIC is enabled by writing a 1 to the Enable bit in the Control A register (CTRLA.ENABLE). The EIC is disabled by writing CTRLA.ENABLE to 0. The EIC is reset by setting the Software Reset bit in the Control register (CTRLA.SWRST). All registers in the EIC will be reset to their initial state, and the EIC will be disabled.

The EIC must be initialized in the following order:

1. Enable CLK_EIC_APB
2. If required, configure the NMI by writing the Non-Maskable Interrupt Control Register (NMICTRL)
3. Enable GCLK_EIC or CLK_ULP32K when one of the following configurations is selected:
   • the NMI uses edge detection or filtering
   • one EXTINT uses filtering
   • one EXTINT uses synchronous edge detection
   • one EXTINT uses debouncing
4. Configure the EIC input sense and filtering by writing the Configuration n register (CONFIG).
5. Optionally, enable the Asynchronous mode.
6. Optionally, enable the Debouncer mode.
7. Enable the EIC by writing a 1 to CTRLA.ENABLE.

The following bits are enable-protected, meaning that they can only be written when the EIC is disabled (CTRLA.ENABLE=0):

• Clock Selection bit in Control A register (CTRLA.CKSEL)

The following registers are enable-protected:

• Event Control register (EVCTRL)
• Configuration n register (CONFIG)
• External Interrupt Asynchronous Mode Register (ASYNCH)
• Debouncer Enable register (DEBOUNCEN)
• Debounce Prescaler register (DPRESCALER)

Enable-protected bits in the CTRLA register can be written at the same time when setting CTRLA.ENABLE to 1, but not at the same time as CTRLA.ENABLE is being cleared. Enable protection is denoted by the "Enable-Protected" property in the register description.

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SAM L10 Code Example

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SAM L11 Code Example

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