The System PLL (Phase-Locked Loop) has a user-selectable input divider, multiplier, and output divider, to provide a wide range of output frequencies. The oscillator circuit will consume more current when the PLL is enabled.
System PLL Input Selection
On reset the System clock setting is copied to the Current Oscillator (COSC) setting. COSC determines the input to the PLL.
The input to the System PLL can be changed at run-time, but the input divider can not. If you want to change the input to the System PLL at run-time, POSC must be 8 to 10 MHz. This is needed to satisfy the PLL multiplier input requirements (4 to 5 MHz) for both FRC and POSC inputs.
The default input can be configured at program time using #pragma statements and the MPLAB® Harmony functions can be used to configure it at run-time.
// Default input is Fast RC Oscillator with the System PLL #pragma config FNOSC = FRCPLL // Default input is Primary Oscillator with the System PLL #pragma config FNOSC = PRIPLL //Run-time configuration using Harmony functions shown below ... // PLL input is FRC PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_FRC_WITH_PLL); // PLL input is POSC PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_PRIMARY_WITH_PLL);
System PLL Input Divider
The input divider must be chosen such that the resulting frequency applied to the PLL multiplier is between 4 and 5 MHz. The input divider options are as follows:
÷1, ÷2, ÷3, ÷4, ÷5, ÷6, ÷10, ÷12
The default divide value is programmable but it can not be changed at run-time.
// default PLL input divider = 1 #pragma config FPLLIDIV = DIV_1 // default PLL input divider = 12 (max) #pragma config FPLLIDIV = DIV_12
System PLL Multiplier
The multiplier options are as follows:
x15, x16, x17, x18, x19, x20, x21, x24
// default PLL multiply = 15 #pragma config FPLLMULT = MUL_15 // default PLL multiply = 24 #pragma config FPLLMULT = MUL_24 ... // run-time config sets PLL multiplier to 15 PLIB_OSC_SysPLLMultiplierSelect(OSC_ID_0, 15);
System PLL Output Divider
The System PLL output clock divider options are as follows:
÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷256
Ensure the output is less than or equal to the maximum device frequency (see specific device data sheet).
// default PLL output divider = 2 #pragma config FPLLODIV = DIV_2 // default PLL output divider = 32 #pragma config FPLLODIV = DIV_32 ... // set PLL output divider to 2 PLIB_OSC_SysPLLOutputDivisorSet(OSC_ID_0, OSC_SYSPLL_OUT_DIV_2);
System PLL Lock Status
The System PLL requires some time to achieve lock when a clock source is first applied. The SLOCK Status bit can be checked to determine if enough time has passed to ensure a stable PLL output.
When the clock input to the PLL is changed, the hardware automatically clears this bit. After the PLL start-up timer has expired, the bit is automatically set. Please refer to the specific device data sheet for PLL lock time ("TLOCK" = 2 ms max).
The PLL lock status bit will be set upon the expiration of the timer even if the PLL has not achieved a lock. If the PLL does not stabilize during start-up, SLOCK may not reflect the status of the PLL lock, nor does it detect when the
PLL loses lock during normal operation.
The following MPLAB® Harmony function returns the state of the PLL lock status. You are responsible for checking this status anytime you change the input to the System PLL.
// variable to hold the status of PLL lock bool clockPLL_st; // function returns value of PLL lock status clockPLL_st = PLIB_OSC_PLLClockIsLocked(OSC_ID_0);