There are a couple of points to keep in mind when configuring the phased-locked loop (PLL) sub-system for the System Clock.
The input to the PLL must be between 4MHz and 5MHz.
Divider x resides in the configuration bit area and cannot be modified during run time!!! Look for FPLLIDIV in the Oscillator Family Reference Manual. It can be set from ÷1 to ÷6, ÷10 or ÷12.
The PLL multiplier is configurable (x15 through x21 or x24 – see PLLMULT). The Divider y can then divide the output down again so that the output frequency lies at or under 80MHz (from ÷1 to ÷256 in steps of powers of 2).