Exception Mechanism

On MIPS®-based CPUs, such as the PIC32MZ family of processors, peripheral/external interrupts, traps, system calls, and everything else that can disrupt the normal flow of execution are called exceptions and are handled by a single mechanism.


Exceptions are classified into 2 major types: expected and unexpected:

  • Expected: Resulting from normal (i.e. expected) operations, such as
    • Peripheral/External Interrupts
    • WDT wakeup
    • Debug break-points
    • System calls
  • Unexpected: Resulting from error (i.e. unexpected) conditions such as
    • Hardware-detected errors, such as integer overflow or divide-by-zero
    • Illegal user-mode operations
    • Bus error (addresses generated beyond physically implemented memory)

The main difference between Expected/Unexpected exceptions is that an Unexpected exception cannot be enabled/disabled (like a traditional "Non-Maskable" Interrupt (NMI)), while an Expected exception can be.

Unexpected exceptions resulting directly from the execution of the program are referred to as Execution Exceptions, or simply as Traps, for example:

  • execution of instruction causing integer overflow or undefined result (ex. divide by 0)
  • execution of the trap instruction
  • a reserved or undefined opcode is executed

All exceptions are handled similarly in that the current instruction flow is changed temporarily to execute special procedures to handle the exception.

When an exception is detected, the CPU Execution Unit does the following:

  • The address of the next instruction to execute after the handler returns is saved into the EPC register of Coprocessor0 (CP0).
  • The CP0 CauseEXCCODE bit-field is updated to reflect the reason for exception or interrupt.
  • The CP0 StatusEXL or StatusERL bit is set to cause Kernel mode execution.
  • An exception handler entry point address is obtained based on the type of exception and the current state of the processor (CP0 Statusxxx bits).
  • Automated Interrupt Epilogue can save some of the CP0 state in the stack and automatically update some of the CP0 registers in preparation for interrupt handling.
  • Processor starts execution from the exception handler's entry point address.

Interrupt Controller

As shown above, the PIC32MZ generates interrupt exception requests in response to interrupt events coming either from the peripheral modules the CPU Core (Core Timer, Performance Counter, Fast Debug Channel).

The Interrupt Controller module exists external to the CPU Execution Unit and prioritizes the interrupt events before presenting them to the CPU. The module includes the following features:

  • Up to 256 interrupt sources
  • Single and Multi-Vector mode operations
  • Up to five external interrupts with edge polarity control
  • Interrupt proximity timer
  • Seven user-selectable priority levels for each vector
  • Four user-selectable sub-priority levels within each priority
  • User-configurable shadow set based on priority level (this feature is not available on all devices; refer to the “Interrupt Controller” chapter in the specific device data sheet for availability)
  • Software can generate any interrupt
  • User-configurable Interrupt Vector Table (IVT) location
  • User-configurable interrupt vector spacing

Exception system configuration is managed through 2 sets of control registers:

  • One in the Interrupt Controller,
  • And the other in the CPU Coprocessor0 (CP0) register set.

To avoid confusion, The PIC32MZ family documentation provides a typographic distinction for these registers:

  • Interrupt Controller register names are signified by upper-case letters only (i.e. INTSTAT, INTCON)
  • CP0 register names are signified by upper and lower-case letters (i.e. IntCtl, Ebase)
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