Virtual addresses used by software are converted to physical addresses by the CPU's memory management unit (MMU) before being sent to the system bus.
The MMU on PIC32MZ devices with the microAptiv™ or M5150 MPU core perform the following translations:
- Fixed Mapping Translation (FMT) on KSEG0/KSEG1
- Physical Address = Virtual Address & 0x1FFFFFFF
- Programmable Translation using a Translation Lookaside Buffer (TLB) on KUSEG/KSEG2/KSEG3
- Physical Address = TBD (Depends on the specific configuration)
For a typical PIC32MZ application running in Kernel mode, virtual memory segments KSEG0/KSEG1/KSEG2 are used. KSEG0/KSEG1 are trivially mapped as indicated above, while the MPLAB XC32 compiler start-up code initializes the TLB to map external serial (SQI) and parallel (EBI) memory interfaces into KSEG2.
PIC32 devices with the microAptiv™ or M5150 MPU core include a Memory Management Unit (MMU) that uses a Translation Lookaside Buffer (TLB) to translate a virtual page address to a physical page address. This feature is used by operating systems to manage multiple tasks running in the same virtual memory, by mapping them into separate physical memory locations. The MMU can also provide protection of physical memory areas and define the cache protocol. PIC32 devices with the microAptiv™ or M5150 MPU core support page sizes from 4 KB to 1 MB.
Please refer to Section 50. CPU for Devices with MIPS32® microAptive™ and M-Class Cores (DS60001192) for detailed coverage on the TLB.
Also, see chapter 6 of See MIPS Run for a good discussion on low-level memory management and the TLB in MIPS® CPUs.