Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) monitors the Primary Oscillator (POSC) to ensure it is functional. If the POSC stops working, it will automatically switch the clock source to the internal Fast RC Oscillator (FRC) (or Backup FRC (BFRC) if available). The switch to the FRC or BFRC allows continued device operation.
The FSCM will generate an interrupt (optional on some devices) and you determine what code runs in that interrupt. You can retry the POSC to see if it recovers, or execute code appropriate for a clock failure.
The following code example shows how to enable the FSCM. It controls the clock switching and monitor (FCKSM) setting in one of the device configuration registers.
// clock switching enabled and clock monitor enabled #pragma config FCKSM = CSECME
All devices have at least one internal FRC oscillator. If your device also has a Backup FRC (BFRC) it will be used as the clock source instead. The BFRC is dedicated to the FSCM and can not be used for anything else.
For more detail on the Fail-Safe Clock Monitor feature, please review the Oscillator family reference manual chapter for that device, for example:
- Section 6. Oscillators (PIC32MX795F512L)
- Section 42. Oscillators with Enhanced PLL (PIC32MZ2048EFG100)
The device data sheet should then be consulted to verify the specific features implemented in that device.