AVR® ADC Differential Mode

A differential Analog to Digital Converter (ADC) measures the voltage difference between two signals. An ADC typically measures the voltage between the signal and ground but in differential mode, the ground pin is actually connected to another part of the circuit so the ADC can measure the difference between the two signals. This is often used to measure a small signal with a large offset. Using a differential input allows the ADC to measure a smaller portion of the signal.

Differential Setup

The differential inputs are run through a gain amplifier to increase the signal size to the converter. Some AVR® devices have pins with adjustable gain. When using differential gain channels, certain aspects of the conversion need to be taken into consideration. Differential channels should not be used with an Analog Reference Voltage (AREF) less than 2 V. On AVR devices, differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC clock. This synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific phase of CKADC2 clock.

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Timing Critical Measurements

On a typical AVR device with differential mode, a conversion you initiate (that is, all single conversions, and the first free running conversion) when CKADC2 clock signal is low will take the same amount of time as a single-ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion you initiate when CKADC2 clock signal is high will take 14 ADC clock cycles due to the synchronization mechanism.

In Free Running mode, a new conversion is initiated immediately after the previous conversion completes, and since CKADC2 is high at this time, all automatically started (that is, all but the first) free running conversions will take 14 ADC clock cycles.

If differential gain channels are used and conversions are started by Auto Triggering, the ADC must be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is started. Since the gain stage is dependent on a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between each conversion (setting the ADEN bit in ADCSRA to then to 1), only extended conversions are performed. The result from the extended conversions will be valid.

Typical Application

Reading the voltage across a resistor with a steady three volt offset is a simple example where a differential input can measure the signal above the DC offset.

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Additional Information

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