AVR Timer Compare Register Double Buffer

AVR® devices have a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and PWM support. It allows accurate program execution timing (event management) and wave generation.

A simplified block diagram of the 8-bit Timer/Counter Output Compare Unit is shown.


Note:  The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B).

Adjustments to the PWM period register value or compare register value can be random in the application. If an update occurs at the same time as a timer compare match occurs, the match may be missed. This can cause the PWM control to hit a max duty cycle of 100% which can cause issues in the control application. For this reason AVR timers have optional double buffers.

Double Buffer Summary


Double Buffer Operation

The Output Compare Registers (OCR0x) are double buffered when using any of the Pulse Width Modulation (PWM) modes. When double buffering is enabled, the CPU has access to the OCR0x Buffer Register. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The double buffered OCR0x are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). The compare match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request.

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