AVR Reset Sources

The AVR device has four sources of reset:

  • Power-on Reset - The Microcontroller (MCU) is reset when the supply voltage is less than the Power-on Reset threshold (VPOT).
  • External Reset - The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length.
  • Watchdog System Reset - The MCU is reset when the Watchdog Timer period expires and the Watchdog System Reset mode is enabled.
  • Brown-out Reset - The MCU is reset when the supply voltage VCC is less than the Brown-out Reset.
avr_reset.png

MCU Status Register (MCUSR)

To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

mcusr.png

Power-on Reset (POR)

A POR pulse is generated by an On-chip detection circuit. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage.

A POR circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in Reset after VCC rise.

The Reset signal is activated again, without any delay, when VCC decreases below the detection level.

powerup.png

Brown-out Detection (BOD) and Brown-out Reset (BOR)

The device has an On-chip BOD circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses.

The BOR circuitry has hysteresis on the detection level. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level (VBOT-) for longer than tBOD. When that occurs, the BOR is immediately activated.

When VCC increases above the trigger level (VBOT+ in the following figure), the delay counter starts the MCU after the Time-out period tTOUT has expired.

bor.png

Watchdog Timer (WDT)

The WDT runs independent of the rest of the system, causing system resets whenever it times out. However, the application software should ensure that the timeout never occurs by resetting the WDT periodically as long as the software is in a known healthy state. If the system hangs or program execution is corrupted, the WDT will not receive its periodic reset, and will eventually time out and cause a system reset.

The Enhanced WDT in some AVR devices also has the ability to generate interrupts instead of resetting the device. Since the WDT runs from its own independent clock, it can be used to wake up the AVR from all sleep modes. This makes it an ideal wake up timer, easily combined with ordinary operation as a system reset source. The interrupt can also be used to get an early warning of an upcoming Watchdog System Reset so that vital parameters can be backed up to non-volatile memory.

Clock Failure Detection (CFD)

The CFD allows the user to monitor the low power crystal oscillator or external clock signal (XOSC). The XOSC is monitored by the CFD circuit operating with the internal 128kHz oscillator. CFD monitors XOSC clock and if it fails, it will automatically switch to a safe internal RC clock. When a Power-On or External Reset occurs, the device will switch back to XOSC clock and continue monitoring XOSC clock for failures.

The safe clock is derived from the 8MHz internal RC system clock. This allows the safe clock to be configured to meet the fail-safe needs of the application.

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