AVR® devices include at least one and sometimes more Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) blocks. In the block diagram of the USART, the Central Processing Unit (CPU) accessible I/O Registers and I/O pins are shown.
USART Block Diagram
The dashed boxes in the block diagram separate the three main parts of the USART:
- Clock Generator
The Clock Generation logic consists of synchronization logic for the external clock input used by synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is only used by synchronous transfer mode.
The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator, and Control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register, and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun, and Parity Errors.
Brief USART Introduction
- Full Duplex Operation (Independent Serial Receive and Transmit Registers)
- Asynchronous or Synchronous Operation
- Master or Slave Clocked Synchronous Operation
- High Resolution Baud Rate Generator
- Supports Serial Frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
- Odd or Even Parity Generation and Parity Check Supported by Hardware
- Data OverRun Detection
- Framing Error Detection
- Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
- Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
- Multi-processor Communication Mode
- Double Speed Asynchronous Communication Mode
- Start Frame Detection
Serial Communication is a way to send data between two electronic devices using just two wires. The USART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a Voltage Output High (VOH) or mark state which represents a ‘1’ data bit, and a Voltage Output Low (VOL) or space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same state stay at the same output level without returning to a zero or neutral level between each bit transmission. The Idle state puts the output pin at a mark (i.e. high state). Transmission can occur in a Synchronous or Asynchronous fashion.
Synchronous Clock Operation
Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode:
- Bidirectional data line
- Clock line
Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The USART can operate as either a master or slave device. Typically Start and Stop bits are not required for synchronous transmissions
When synchronous mode is used (UMSEL = 1), the XCKn pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (RxDn pin) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn pin) is changed.
Asynchronous Data Reception
In Asynchronous communications two pins are used. One is the Transmit (TxDn) and one is the Receive (RxDn). The TxDn of one device is connected to the RxDn of the second device. Each character transmission consists of one Start bit followed by five to nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation:
- Normal asynchronous
- Double Speed asynchronous
- Master synchronous
- Slave synchronous
Clock Block Diagram
- txclk Transmitter clock (internal signal).
- rxclk Receiver base clock (internal signal).
- xcki Input from XCK pin (internal signal). Used for synchronous slave operation.
- xcko Clock output to XCK pin (internal signal). Used for synchronous master operation.
- OSC System clock frequency.
Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The USART Baud Rate Register (UBRRn) and the down-counter connected to it, function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRRn value each time the counter has counted down to zero or when the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRRn+1)).
The table below contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source.