AVR® Watchdog Timer

AVR® devices have an Enhanced Watchdog Timer (WDT) that runs on a separate oscillator from the main instruction clock. The WDT is essentially a counter that increments based on the clock cycles of an on-chip 128kHz oscillator. The WDT forces an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, the application code needs to issue a Watchdog Timer Reset (WDR) instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.

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Brief WDT Summary

WDT Features:

  • Clocked from separate On-chip Oscillator
  • Three operating modes:
    • Interrupt
    • System Reset
    • Interrupt and System Reset
  • Selectable Time-out period from 16 milliseconds to 8 seconds
  • Optional Hardware fuse Watchdog always on (WDTON) for fail-safe mode

Interrupt Mode

In Interrupt mode, the WDT forces an interrupt when the timer expires. This interrupt can be used to wake the device from any of the sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, forcing an interrupt when the operation has run longer than expected. This is enabled by setting the Interrupt mode bit (WDIE) in the Watchdog Timer Control Register (WDTCSR).

System Reset

In System Reset mode, the WDT forces a reset when the timer expires. This is typically used to prevent system hang-up in the case of runaway code. This is enabled by setting the System Reset mode bit (WDE) in the Watchdog Timer Control Register (WDTCSR).

Interrupt and System Reset mode,

Interrupt and System Reset mode combines the other two modes by first forcing an interrupt and then switching to System Reset mode. This mode will offer a safe shutdown by allowing time to save critical parameters before a system reset. This is enabled when both the WDTIE and WDTE are set.

WDT Time-out period

The Watchdog Timer Prescale bits (WDP[3:0]) of the WDTCSR determine the Watchdog Timer delay when the Watchdog Timer is running. The different prescaling values and their corresponding timeout periods are shown in the following table.

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WDTON

The WDTON fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed, the WDE bit and WDIE bit are locked to 1 and 0 respectively.

Watchdog Timer Status Flag

The Watchdog System Reset Flag (WDRF) bit in the MCU Status Register (MCUSR) is set if a Watchdog System Reset occurs. The WDRF bit is cleared by a Power-on Reset, or by writing a '0' to it. To identify a reset condition, the user should read and then reset the WDRF as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

MCU Status Register

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