AVR® Device Peripheral Power Reduction Register

AVR® 8-bit microcontrollers include several sleep modes to save power. The AVR device can also lower power consumption by shutting down the clock, for select peripherals, via a register setting. That register is called the Power Reduction Register (PRR).

Example: Register from ATmega328PB.

Writing a logic one to a bit shuts down the peripheral clock.

  • PRTWI0: Power Reduction TWI0
  • PRTIM2: Power Reduction Timer/Counter2
  • PRTIM0: Power Reduction Timer/Counter0
  • PRUSART1: Power Reduction USART1
  • PRTIM1: Power Reduction Timer/Counter1
  • PRSPI0: Power Reduction Serial Peripheral Interface 0
  • PRUSART0: Power Reduction USART0
  • PRADC: Power Reduction ADC

The PRR provides a run time method to stop the clock to select individual peripherals. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain committed, hence the peripheral should, in most cases, be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module into the same state as before shutdown.

PRR clock shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped.

Brief AVR Power Reduction Register Summary

Project Download: Sample Project Mentioned in Video

Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions that are not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption:

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as an input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode.

Brown-Out Detector

If the Brown-Out Detector (BOD) is not needed by the application, this module should be turned off. If the BOD is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and consequently will always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-Out Detector, the Analog Comparator or the Analog-to-Digital Converter. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately.

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important consideration is to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. If the input buffer is enabled and the input signal is left floating, or has an analog signal level close to VCC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR0 for ADC, DIDR1 for AC).

On-chip Debug System

If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the main clock source is enabled and always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.

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