AVR® Serial Peripheral Interface (SPI)

Serial Peripheral Interface (SPI) protocol on AVR® devices will enable your AVR microcontroller to communicate with multiple other devices at the same time. Use the SPI bus to communicate between a master device and one or multiple slave devices. SPI uses Master In Slave Out (MISO) and Master Out Slave In (MOSI) lines to communicate between devices, the Serial Clock (SCK) to maintain a consistent clock between devices, and Slave Select (SS) line to pick which peripheral device is communicating with the master device.

SPI System

The system consists of two shift registers and a master clock generator. The SPI Master initiates the communication cycle when pulling low the SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the MOSI line, and from Slave to Master on the MISO line. After each data packet, the Master will synchronize the Slave by pulling the SS line high.

spistructure.png

Master Mode

When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable (SPIE) bit in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use.

Slave Mode

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, the software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag (SPIF) is set. If the SPI Interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested.

Additional Information

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