PIC18F Vectored Interrupt Controller Overview

The Vectored Interrupt Controller (VIC) module, found on the latest PIC18F family microcontroller devices, reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU. This module includes the following major features:

• Interrupt Vector Table (IVT) with a unique vector for each interrupt source
• Fixed and ensured interrupt latency
• Programmable base address for IVT with lock
• Two user-selectable priority levels – high priority and Low priority
• Two levels of context saving
• Interrupt state status bits to indicate the current execution status of the CPU

The VIC module assembles all of the interrupt request signals and resolves the interrupts based on both a fixed natural order priority (i.e., determined by the IVT) and a user-assigned priority (i.e., determined by the IPRx registers), thereby eliminating scanning of interrupt sources.

interruptstates.png

Control Registers

The VIC module is set up through the following registers:

INTCON0 Control Register Global interrupt control functions and external interrupts are controlled from the INTCON0 register.
INTCON1 Control Register The INTCON1 register contains the status flags for the Interrupt controller.
Peripheral Interrupt Status (PIRx) Registers The PIRx registers contain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or an external signal and is cleared via software.
Peripheral Interrupt Enable (PIEx) Registers The PIEx registers contain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals.
Peripheral Interrupt Priority (IPRx) Registers The IPRx registers are used to set the Interrupt Priority Level for each source of interrupt. Each user interrupt source can be assigned to either a high or low priority.
IVTBASE<20:0> Address Registers The IVTBASE register is user programmable and is used to determine the start address of the IVT.
IVTLOCK Register The IVTLOCK register is used to prevent any unintended writes to the IVTBASE register.

Configuration Settings

There are two configuration bits that control the way the VIC can be configured.

  • CONFIG2L<3>, MVECEN bit - The MVECEN bit determines whether the Vector table is used to determine the interrupt priorities.
  • CONFIG2L<4>, IVT1WAY bit - The IVT1WAY bit determines the number of times the IVTLOCKED bit can be cleared and set after a device Reset.

Additional Operational Detail

For more information on how VIC operate and how to set them up with the MPLAB Code Configurator, refer to the following link:

 
Vectored Interrupts on 8-Bit MCU
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