The Special Event Trigger output starts an A/D conversion (if the A/D module is enabled). This mode can also be used to effectively provide a 16-bit programmable period register for Timer1. The CCPx module does not assert control of the CCPx pin in this mode.
When Special Event Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following:
- Resets Timer1
- Starts an A/D conversion if the ADC is enabled
The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H:TMR1L register pair and the CCPRxH:CCPRxL register pair. The TMR1H:TMR1L register pair is not reset until the next rising edge of the Timer1 clock.
1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register.
2: Removing the match condition, by changing the contents of the CCPRxH:CCPRxL register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset will preclude the Reset from occurring.