The primary purpose of the Complementary Output Generator (COG) is to convert a single output PWM signal into a two output complementary PWM signal. This is similar to the Complimentary Waveform Generator (CWG) on other PIC® Microcontroller devices, but the COG has several other features not seen in the CWG.
The COG can also convert two separate input events into a single or complementary PWM output. The COG PWM frequency and duty cycle are determined by a rising event input and a falling event input. The rising event and falling event may be the same or different source. Sources may be synchronous or asynchronous to the COG reference clock. The rate at which the rising event appears determines the PWM frequency. The time between the rising event input and the falling event input determines the duty cycle.
A selectable clock input is used to generate the optional phase delay, blanking and dead-band times. A simplified block diagram of the COG is shown in Figure below.
When the COG outputs are first enabled, the COGxOUT0 pin is inactive (low) and the COGxOUT1 pin is active (high). This can be reversed with the polarity setting in COGxCON0 register. This is described in the Output Control section below.
The COG module has the following features:
- Synchronous PWM
- Instruction Clock
- System Clock
- Independently selectable rising event input sources
- Independently selectable falling event input sources
- Independently selectable edge or level event sensitivity
- Independent output enables
- Independent output polarity selection
Dead-band control with:
- Independent rising and falling event dead-band times
- Synchronous and asynchronous timing
Auto-shutdown control with:
- Independently selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control (high, low, off, and High-Z)
- Independent rising and falling delay times
- Independent rising and falling event blanking times
Modes of Operation
The COG offers two modes of operation:
- Synchronous PWM Mode
- Push-Pull Mode
The mode is selected by setting (Push-Pull) or clearing (Synchronous) the GxMD bit of the COGxCON0 register.
Synchronous PWM Mode
In synchronous PWM mode, the COG generates two complementary PWM waveforms derived from the rising and falling event sources. In the simplest configuration, the rising and falling event sources come from the same signal, such as a PWM signal (CCP1 Peripheral). The COG converts this single PWM input into a dual complementary PWM output. The frequency and duty cycle of the dual PWM output match those of the single input PWM signal. The rising edge of the PWM input will trigger the rising edge of the COGxOUT0 output pin. The falling edge of the PWM input will trigger the falling edge of the COGxOUT0 pin. The COGxOUT1 will be the complimentary output of the COGxOUT0.
A typical waveform is shown below.
The event transition of each output can be delayed from the on-to-off transition relative to the other output, thereby creating a time when neither output is driven. This is referred to as dead-band time and this is adjustable in the COG module. There is also a phase delay that can create a time delay before both signals change their state after an event transition. Both Dead Band and Phase Delay are shown below and are detailed below.
In Push-Pull mode, the COG generates a PWM pulse on the COGxOUT0 pin on every odd numbered incoming pulse rising edge events. The COGxOUT1 pin produces the same pulse on every even numbered incoming pulse.This creates an alternating set of signals produced from the single input source. An example is shown below.
The COG offers several input sources to generate the complementary waveform. One event can trigger the rising portion of the output and a separate event can trigger the falling portion. These event inputs can be independently connected to the Rising Event control block or the Falling Event control block. This list may vary from device to device. The list below is from the PIC12F753:
- HLTimerx (Hardware Limit Timer)
- Timer2 = PR2 (Timer2)
- CCPx (Capture/Compare/PWM)
- CxOUT (Comparator Output)
- COGxFLT (COG Output)
The rising event input source is selected using bits in the COGxRIS register.
The falling event input source is selected using bits in the COGxFIS register.
All the rising inputs are OR'd together to produce the rising event signal.
All the falling inputs are OR'd together to produce the rising event signal.
Edge or Level Detection
The event inputs detection can be level-sensitive or edge-sensitive.
For quick changing input events such as a square wave, the edge-sensitive mode is used. Otherwise the rapidly rising or falling signal will cause the COG output to switch states. A level sensitive mode will wait until the signal has reached a voltage threshold before the COG output state switches. This level is described in the data sheet electrical specification section for the device you are using.
This detection mode is set for each input in the COGxRSIM or COGxFSIM register.
The COG module allows for one of three clock sources to be selected:
- Fosc (System Clock)
- Fosc/4 (Instruction Clock)
- HFINTOSC (16 MHz only)
The clock sources are selected using the GxCS<1:0> bits of the COGxCON1 register.
The COG features that use this clock source are listed below.
- Rising and falling dead-band time
- Rising and falling blanking time
- Rising and falling event phase delay
Output Pin Enable
Each COG output pin has individual output pin enable control. Output enables are selected with the GxOE0 and GxOE1 bits of the COGxCON0 register. When an output pin enable is cleared, the COG has no connection to the output pin. When the output enable is set, the override value or active PWM waveform is applied to the pin per the internal port priority selection.
The COG function can be completely disabled by clearing the GxEN pin in the COGxCON0 register.
The polarity of each COG output can be selected independently. When the output polarity bit is set, the corresponding output is active high. Clearing the output polarity bit configures the corresponding output as active low. However, polarity does not affect the override levels. Output polarity is selected with the GxPOL0 and GxPOL1 bits of the COGxCON0 register.
Dead-band control provides for non-overlapping output signals, to prevent shoot through current in power switches. The COG contains two separate dead band timers. One is for the rising edge and one is for the falling edge.
Dead-band is timed by one of two methods:
- Synchronous Counter mode
- Asynchronous Counter mode
The mode is selected by the GxRDBTS (rising edge) bits and GxFDBTS (falling edge) bits in the COGxCON1 register.
Synchronous Counter Dead-Band Delay
The Synchronous Counter uses the COG clock source to create a delay. A value is placed in the dead-band count register indicating how many clock periods to delay. The value is a four bit binary value set in the COGxDBR (Rising Edge) or COGxDBF (Falling Edge) register. Being a four bit value, the count is limited to 0 to 15 periods.
Asynchronous Counter Dead-Band Delay
The Asynchronous Counter uses the COG clock source to create a delay. A value is placed in the dead-band count register indicating how many five nanosecond delay elements to wait. The value is a 4 bit binary value set in the COGxDBR (Rising Edge) or COGxDBF (Falling Edge) register. Being a 4 bit value the count is limited to 0 to 15 delay elements.
Auto-shutdown is a method to immediately override the COG output levels with specific settings that allow for
safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by
The shutdown state can be entered by either of the following
- Software generated
- External Input
Setting the GxASDE bit of the COGxASD0 register will force the COG into the shutdown state. When auto-restart is disabled, the shutdown state will persist as long as the GxASDE bit is set. When auto-restart is enabled, the GxASDE bit will clear automatically and resume operation on the next rising edge event.
External shutdown signals provide the fastest way to safely suspend COG operation in the event of a Fault condition. When any of the selected shutdown signals goes active, the COG outputs will immediately go to the selected override levels without software delay.
Any combination of available shutdown signals can be selected to cause a shutdown condition. The shutdown signals offered may vary with the device being used but those shutdown sources are selected by bits in the COGxASD1 register.
For example, the PIC16F753 offers these input sources for shutdown control. Any combination of these inputs enabled are or'd together to produce the shutdown signal.
- COG1FLT Pin
Pin OverRide Levels
The output signals from the COG can be driven to a selected state during shutdown. This is controlled with bits in the COGxASD0 register. The pin can be set in one of four states:
- Forced Low
- Forced High
- PWM Inactive State (same as state caused by a falling event signal)
While dead-band delay can create a non-overlapping COGxOUT0 and COGxOUT1 signals, there may be times when both signals need to be delayed, between transitions, at the same time. This is where the Phase Delay feature is used. The delay can be implemented on either or both the rising input event and falling input event. This is accomplished by placing a count value in COGxPHR (rising) or COGxPHF (falling) phase delay count register.
The delay begins timing off the rising and/or falling input event signal. Similar to the Dead-Band Synchronous mode, the delay length is based on the number of COG clock periods to wait as defined in the COGxPHR or COGxPHF bits. This can be a value from 0 to 15. So the minimum delay is zero clock periods, or no delay, up to a maximum of 15 clock periods. The actual maximum timing delay will depend on the clock source selected and the time it takes for one period of the clock.
In the example below, the COGxPHR (rising) register is set to delay 7 clock periods after the rising input event.
Input blanking allows inputs to be masked or ignored for a short period of time. This can be used to prevent electrical transients, such as those caused by the turn-on/off of power components, from generating a false input event.
The COG contains two blanking counters: one triggered by the rising event and the other triggered by the falling event. The counters are cross-coupled with the events they are blanking. The falling event blanking counter is used to blank rising input events and the rising event blanking counter is used to blank falling input events. Once started, blanking extends for the time specified by the corresponding blanking counter. Blanking is timed by counting COG_clock periods from zero up to the value in the blanking count register.
Operation During Sleep Mode
The COG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. The HFINTOSC remains active during Sleep, provided that the COG module is enabled, the input source is active, and the HFINTOSC is selected as the clock source, regardless of the system clock source selected.
In other words: if the HFINTOSC is simultaneously selected as the system clock and the COG clock source, then when the COG is enabled and the input source is active the CPU will go idle during Sleep, but the COG will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current.