8-bit PIC® MCU Timer0

Last modified by Microchip on 2023/11/22 16:33

The Timer0 module is an 8-bit timer/counter that is included with all 8-bit PIC® MCU devices. The Timer0 is more than just a timer. It has all the following features:

  • 8-bit timer/counter register (TMR0)
  • 8-bit prescaler (independent of Watchdog Timer)
  • Programmable internal or external clock source
  • Programmable external clock edge selection
  • Interrupt on overflow
  • TMR0 can be used to gate Timer1

Below is a simplified block diagram of the Timer0 module:

simplified Timer0 module block diagram

The Timer0 module can be used as an 8-bit timer. In timer mode, it is incremented on every instruction clock pulse unless a prescaler is used to reduce the speed. The TMR0 register can be written via software to preload it with a value. If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. This can be adjusted in the prewritten value.

Timer Mode

Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register.

OPTION_REG register TMR0CS bit graphic

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Software Programmable Prescaler

A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register.

OPTION_REG register PSA bit graphicOPTION_REG register prescaler rate select bits graphic

The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. The prescaler is exclusively shared between the Timer0 module and the Watchdog Timer. When the prescaler is assigned to the Timer0 module, any write to the TMR0 register will immediately update the TMR0 register and clear the prescaler.

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Counter Mode

In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI I/O pin. This allows the PIC® MCU to count pulses from an external clock source. The signal has voltage limits as specified in the device data sheet but will typically be the limits of the device's operating voltage.

By selecting this externally triggered counting option to Timer0, the software can monitor the pulses from an external sensor to capture data. Timer0 has a 255 count limit before overflowing back to zero. This count can be extended by using a prescaler.

Counter Setup

8-bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’.

OPTION_REG register T0CKI pin selection graphic

The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register.

OPTION_REG register TMR0SE bit graphic

Counter Mode Synchronization

When an external clock input is used for Timer0, it must meet certain timing requirements. These requirements ensure the external clock can be synchronized with the internal instruction clock. Also, there may be a slight delay in the actual incrementing of Timer0 after synchronization.

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output. The T0CKI signal has to be at a high level for at least two clock periods of the system clock (Fosc) and a small RC delay of 20 nanoseconds. The signal must also be low for at least two Fosc clock periods.

When a prescaler is used, the external clock input is divided by an asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external TOCKI input to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI signal to have a period of at least four clock periods of the Fosc clock (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse-width requirement for the device (around 10 nanoseconds).

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Timer0 Interrupt

The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows from FFh to 00h, regardless of whether or not the Timer0 interrupt is enabled. This allows the software to poll the bit asynchronously. The TMR0IF bit is not automatically reset, it needs to be cleared in the software.

To enable the automatic interrupt, the Timer0 interrupt enable bit (TMR0IE) of the INTCON register must be set to '1'.

With the interrupt enabled, when the TMR0 register overflows, the CPU will direct execution to the interrupt vector which needs to hold the address of the software interrupt routine. When the overflow occurs, the Interrupt Service Routine (ISR) can preload the TMR0 register and then clear the TMR0IF bit.

INTCON register graphic

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Timer0 Operation During Sleep

Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.

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