Analog-to-Digital Converter (ADC) Acquisition Time
Analog-to-Digital Converter (ADC) Acquisition Time - Successive Approximation Register (SAR) ADC
Acquisition time (sampling time) is the time required for the Analog-to-Digital Converter (ADC) to capture the input voltage during sampling. The acquisition time of a Successive Approximation Register (SAR) ADC is the amount of time required to charge the holding capacitor (CHOLD) on the front end of an ADC. Internally, the track-and-hold circuit is implemented as a charge-holding capacitor that is disconnected from the analog input pin just before the Analog-to-Digital conversion begins. The holding capacitor must be given sufficient time to settle to the analog input voltage level before the actual conversion is initiated. If sufficient time is not allowed for acquisition, the conversion will be inaccurate. The required acquisition time is based on a number of factors: holding capacitor value (CHOLD), the impedance of the internal analog multiplexer, The output impedance of the analog source (RSOURCE), and the switch impedance (RSS). The figure below shows a typical model for the analog input of a SAR ADC. The input model parameters will vary, so the designer should refer to the device datasheet to ensure that the proper acquisition time is provided based on the input circuit that is used in the design.
An increase in the source impedance will increase the required acquisition time. In addition, there is a maximum recommended source impedance requirement. Generally speaking, the maximum source impedance requirement for an 8-bit or 10-bit ADC is in the range of 10 kΩ; for 12-bit ADCs, it is 2.5 kΩ. Design engineers need to refer to the specific device datasheet with regard to the equation that calculates the minimum acquisition time for your particular application.
ADC Acquisition Time - Pipeline ADC
To start sampling with a pipeline ADC, depending upon the ADC's datasheet, either the rising or falling edge of the external input clock signal initiates the ADC sampling (acquisition). For each conversion, the pipeline ADC samples the signal once.
ADC Acquisition Time - Delta-Sigma ADC
The acquisition time of the Delta-Sigma ADC takes longer than SAR or pipeline ADC because it averages multiple samples for each conversion (oversampling). This averaging is done in the form of a Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) digital filter. The oversampling mechanism and acquisition time of Delta-Sigma ADCs vary from device to device.
ADC Conversion Time
Conversion time is the time required to obtain the digital result, i.e., the time it takes to complete a single conversion. Conversion time does not include the acquisition time or the ADC setup time. The conversion time is usually specified in analog-to-digital clock cycles and the minimum period for the clock is specified to obtain the specified accuracy for the ADC.
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