A debugger, emulator and programmer use a serial signaling scheme to program a target device in-circuit. A debugger and emulator use the same scheme to debug a target device in-circuit.The signals utilized are the clock and data signals defined in some data sheets as PGC and PGD or ICSPCLK and ICSPDAT. Additionally, MCLR/Vpp is used as either a high voltage programming signal or an attention indicator to the device.
These signals are not dedicated for programming and debugging only, but are shared with a port pin or alternate peripheral. Generally, most devices use ports RB6 and RB7 as the default primary ports.
For trouble-free in-circuit programming and debugging, you must plan carefully to avoid any problems during the application development or production phase of the product. The proposed implementations are discussed in the following sections.
Recommended ICSP Implementation Configuration
The signals PGC and PGD are active bidirectional signals driven by the tool and target device during a typical programming or debugging session. These signals follow the programming specification and device algorithm. To minimize programming times, the signals are clocked at a fast rate of speed. Any additional obstructions or loads can distort the signals sufficiently enough to cause either intermittent or hard failures and prevent programming.
Keep these signals free of any other passive circuits or active logic in the application. This will ensure trouble-free debugging and programming sessions.
Another benefit of this configuration is that cable length and/or type may be negligible as there will be fewer reflections from cable mismatches.
Additionally, the MCLR/Vpp signal is used by the development tool to provide the voltage used for programming some devices or to signal attention. In instances where the application has a large capacitor, it will cause the signal rise and fall time to degrade. This will hinder the ability of the tool and the device to communicate effectively.
It is recommended to keep the signal pulled up to VDD with a 10K resistor and to utilize the power-on timer features of the device to ensure a proper power-up sequence.
The ICSP power connection from the tool to the target device assembly must use the operating Vdd voltage of the device, not the system. For example, if the system voltage is 5V but the device voltage is 3.3V, then the ICSP power connection should be 3.3V.
A matching operating voltage is required so that logic levels remain compatible between both the development tool and target device.
Alternate ICSP Implementation Configuration
In some cases, especially with low pin count devices, the pins must be utilized by the application.
If this is the case, as a minimum, a resistive isolation is required between the device and the application active node. This will ensure that both the application circuit and the development tool are able to drive the programming pins (PGC and PGD) to ground and to the proper VDD levels. The figure below depicts this configuration.
Figure: Alternate ICSP™ Application Circuit
The resistive isolation value will differ depending on the application and how it is being used. Values ranging from 1K to 10K are suggested. In any case, ensure the levels on PGD and PGC can be driven to their appropriate logic voltage levels.
For isolating MCLR/Vpp, especially when the application uses a voltage supervisor, refer to technical brief TB087 (DS91087) for an in-depth discussion.