What should be done with the PSPCFG0 pin when the ENC424J600 is in SPI mode?

The description on what to do with this pin can be found in the "SPI" section of the ENC424J600/624J600 datasheet:

"When the SPI interface is enabled, all PSP interface pins (except PSPCFG2 and PSPCFG3 on ENC624J600 devices) are unused. They are placed in a high-impedance state and their input buffers are disabled. For best ESD performance, it is recommended that the unused PSP pins be tied to either VSS or VDD. However, these pins may be left floating if it is desirable for board level layout and routing reasons."

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