dsPIC33/PIC24 - ECAN, FNRB (FIFO Next Read Buffer Pointer bits) Not Resetting as Expected

When the CAN FIFO is configured with the following settings:
FSA = b01000; // FIFO Starts at Message Buffer 8
DMABS = 0b000; // 4 buffers in DMA RAM,
the FNRB pointer is not resetting back to buffer 8 after receiving of 4 messages, it continues to increment up to value 32. Why does this happen?

This configuration of FSA and DMABS is invalid. The FIFO Start buffer (FSA) address must be less than or equal to the FIFO End buffer. DMABS defines DMA Buffer Size, as well as the FIFO End buffer: FIFO End buffer = DMA Buffer Size - 1.

Choose a value for the FSA less than or equal to the FIFO End buffer. The valid range, in this case, is FSA = b00000 … b00011.

For more information, please search Microchip's Reference Manual page for the "dsPIC33E/PIC24E FRM, Enhanced Controller Area Network (ECAN)" document.

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