Architecture (ver 1.00)

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 Summary

Microchip 8-bit MCU Families

8bit-family.png

The PIC®16F1xxx Enhanced Mid-Range 8-bit PIC MCU Family spans a wide array of memory sizes and I/O pins.
This page presents the key architectural features of the PIC16F1xxx family of MCUs. Links are provided on this page to the technical details needed to implement applications on the enhanced mid-range PIC MCU family.

Harvard Architecture

Enhanced mid-range PIC MCUs use a dual-bus Harvard Architecture.

Instruction Bus

Program instructions are fed into the ALU from FLASH program memory via the 14-bit instruction bus. On every instruction clock cycle, one 14-bit program word is read into the ALU.

Data Bus

An 8-bit data bus connects the ALU to the data memory. During each instruction, the ALU can read data from the data memory, modify the data, then write the data back to memory.

Instruction Pipelining

This PIC's dual-bus architecture provides for a two-stage instruction pipeline. On each clock cycle, two instruction phases execute:

  1. The next instruction is fetched from program memory
  2. The current instruction is executed and reads/modifies/writes data memory (if needed)

Memory Mapped Peripherals

A closer look at the data memory show the registers controlling the peripherals and the I/O ports accessed by reading or writing to specific data memory addresses. This mapping of peripherals to the memory address greatly simplifies learning how to program this PIC MCU.

The Data Memory page of the Enhanced Mid-Range Tutorial offers a complete description along with program examples accessing the memory mapped peripherals.

Orthogonal Instruction Set

These PIC MCUs each have 49 instructions. Instructions directly accessing data memory addresses execute in one instruction cycle. Instructions which cause a change in the program counter (BRA, GOTO, RETURN, CALL, etc.) take two instruction cycles to execute.

By mapping the I/O and peripheral registers to memory addresses, PIC MCUs do not need special instructions for I/O operations to set peripheral registers. Writing to an I/O port or configuring a peripheral is a simple "write-to-a-memory-location". Reading the value of an input pin, ADC result register, or timer is a simple "read-off-a-memory-location". By using a small number of orthogonal instructions, enhanced mid-range PIC MCUs are easy to program, use less silicon to build, and consume less power.

Examples of Instruction Implementation

For a detailed list of the instruction set and a full discussion of instruction timing, please read the Instruction Set page of the Enhanced Mid-Range Tutorial.

Flexible Clocking Options (Up to 32MHz)

Selected by the PIC MCU's configuration bits, the system clock has the following properties:

  • Optional source - Internal oscillator or external circuitry
  • Flexible speed options - Up to 32MHZ
  • Two-speed start-up - Allow system to run initialization software while the external oscillator is stabilizing
  • Clock Switching - Switch between external and internal clock sources via software
  • Fail-Safe Clock Monitor - Switch to internal oscillator in the event of an external clock failure.
  • [[include :xsi:image:svg |file=mcu1102:architecture-ver-1-00/harvard_3.svg |width=800px]]

For a detailed description of the oscillator configuration options please refer to the 8-bit Oscillator page in the Enhanced Mid-Range Tutorial.

Digital I/O

Almost every pin on the Enhance Mid-Range PIC MCU can be used as a digital input or output pin. Digital Pins share these attributes:

  • Monitor Digital Inputs
  • Control Digital Devices
  • Internal Weak Pull-ups
  • Multiplexed with Peripherals
  • High Drive capability (up to 25 mA sink/source on many I/O pins)
  • Direct single cycle bit manipulation
  • 4kV ESD protection diodes

At Reset:

  • Digital Pins revert to input (Hi-Z)
  • Analog Capable pins revert to analog

Typical Digital Pin Structure

Five registers control the operation of the digital pin. These 8-bit registers control 8 pins of a PORT. Using the registers TRISX, PORTx, LATx, WPUx, and ANSEL the program can:

  • Configure the pin as an input or output TRISx
  • Read an input pin (or all 8 PORT pins) PORTx
  • Output a 1 or to a pin LATx
  • Enable or disable the internal pull-up resistor WPUx
  • Determine if analog capable pins operate in analog or in digital mode ANSEL
  • [[include :xsi:image:svg |file=8bit:emr-architecture/basic_digital_io.svg |width=800px]]

For a complete discussion on digital I/O, including details on programming digital input and output operations refer to the Digital IO page of the Enhanced Mid-Range Tutorial.

Multiplexed Pins

In addition to being configured as digital I/Os, pins on enhanced mid-range PIC MCUs can have several possible functions. The pin diagram on the datasheet shows the options for each pin. At start-up, the program has the option of configuring the pins.

For comprehensive discussion of the enhanced mid-range PIC digital I/O including details on configuring the pins refer to the Peripheral page of the Enhanced Mid-Range Tutorial.

Advanced Peripherals

In addition to digital I/O enhanced mid-range PIC MCU family members have an assortment of advanced peripherals. These peripherals include peripherals for data conversion, communication, and signal conditioning.

For a complete list of peripherals available please refer to the Peripheral page of the Enhanced Mid-Range Tutorial.

Interrupts

Enhanced mid-range PIC MCUs utilize a single vector pre-emptive interrupt structure.

Each peripheral on the PIC is capable of generating an interrupt request. When an interrupt request occurs and interrupts for the requesting device are enabled an interrupt will occur.

The PIC uses a 16-level hardware stack to store the current content of the PC when an interrupt occurs. The program context is saved in shadow registers and control is passed to program memory address 0x04.

Interrupt Service Routine (ISR)

You are responsible for writing the code to service the interrupt and placing the code at address 0x04. This ISR determines the source of the interrupt, then performs the necessary task to service the interrupting peripheral. An ISR's final instruction is the Return From Interrupt (RETFIE) instruction.

Automatic Context Saving

The following registers are saved to a single-level shadow register set in the event of an interrupt

  • W
  • BSR
  • STATUS
  • FSR
  • PCLATH

When the ISR executes the RETFIE instruction, these registers are restored to the pre-interrupt value.

Single Level Interrupt Pre-emption

When an interrupt occurs the Global Interrupt Enable bit (GIE) in the status register is disabled. This will prevent the an interrupt from being pre-empted by another interrupt.

Upon executing a RETFIE the state of the GIE control bit is restored to its pre-interrupt value.

For a complete description of the interrupt process and programming examples please refer to the Interrupt Section of the Enhanced Mid-Range Tutorial.

What happens at System Start-up (RESET)

There are several sources of a RESET on the enhanced mid-range PIC MCU. The RESET sources common to almost all applications are the Power On Reset (POR) and Brown Out Reset (BOR) due to a sagging power supply voltage (i.e. brown-out). There are several other methods for resetting the MCU including Watchdog timeout and directly accessing the MCLR pin.

Program Counter is set to 0x00.

After a RESET the instruction located at address is the first instruction executed. You are responsible for placing code into this address to boot-up the PIC MCU. Microchip's MPLAB® XC8 compiler will insert the appropriate instructions to start-up the PIC and transfer control to main. Assembly level programmers will have to write the code to initialize the PIC and jump past the interrupt vector located at address 0x04.

All Special Function Registers are set to a Default Value

The datasheet for each enhanced mid-range PIC MCU shows the values which the registers will contain at RESET.

sample-register.png

The Programming Examples section of the Enhanced Mid-Range Tutorial provides examples of how to boot-up the PIC MCU.

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