Creating an extra PWM using the CLC


Oftentimes, it can be very useful to have peripherals that can interact with one another on a Microcontroller (MCU) to create extra or new and unique peripherals. The Configurable Logic Cell (CLC) combines up to four input signals from a range of sources, in one of six logic functions, to create an entirely new output signal capable of running other peripherals or I/O pins, even without using a single line of written code. This allows you to create entirely new modules. This tutorial runs an SR Latch using two timers to produce a Pulse Width Modulation (PWM) output on an I/O pin.

Timer2/4/6 modules are a series of 8-bit timers, meaning they count between 0x00 and a post-scaled output value chosen by the user, up to 0xFF. In Free Running Period mode, the timer counts up to the period value, sending a one-clock cycle long pulse and then resetting to 0x00. However, Microchip has expanded this timer series to include Hardware-Limit Timer capabilities, which provides some additional functionality that does not require CPU usage or written code. In this tutorial, you will take advantage of Monostable mode, in which the timer counts up to its defined period value, but then triggers an ON bit, sending out a HIGH pulse, until an external trigger resets the timer.


We will be using Timer 2 and Timer 4 to set the timing base for our PWM signal and we will use the CLC as an SR Latch to combine the timing signals to create the custom signal. Timer 2 is running in Free Running Period mode and will be connected to the SET of the latch. The pulse triggers a 1 out of the SR Latch, while simultaneously setting the Timer 4 LOW. Timer4 is connected to the RESET input of the Latch and drives the PWM LOW after its period value. The figure below shows this visually:



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To follow along with these steps, MPLAB® Xpress should be open and you should be logged in so that the MPLAB Code Configurator plug-in can be used. If you are unfamiliar with the MPLAB Code Configurator you may wish to first complete the Introduction to MPLAB Code Configurator tutorial here. To start, you should see a window that looks like the figure below:



Task 1

This project uses two timers. The first timer we will use is an 8-bit timer called Timer 2 in Free-Running Period mode. Timer 2, Timer 4 and Timer 6 are all also capable of being used as Hardware Limit Timers, which adds two additional modes: Monostable and One-Shot mode. I will explain Monostable mode in more detail in the Timer 4 section of this tutorial, but you can find a complete overview of the Timer 2, 4 and 6 MCC usage here. The datasheet for the PIC16F18855 also contains detailed information about each mode.

From the same Device Resources list choose Timer 2 from below the Timer drop down menu. The Timer 2 easy setup window should now be visible. Change the clock to LFINTOSC (low frequency internal oscillator) which will greatly increase the range of the period value. We will use this for both timers so that we can keep the signals consistent. Set the Prescaler to 1:128 to increase the range of the Timer Period. Finally, set the Timer Period to 1 s. The window on your computer should look similar to the one below:



Similar to the previous peripheral, pick Timer 4 from underneath the Timer drop down menu in Device Resources. Timer 2 will be used for our period, while Timer 4 will become our pulse width value. In order to create an accurate PWM, we want to make sure that the two timers are in sync by using Timer 2 to trigger Timer 4’s reset. Change the Ext RESET Source to TMR2_postscaled.

Next, as mentioned above, we are going to change the Control Mode to Monostable. In Monostable mode, the timer will count to whatever the period of the timer is. Once the timer counts up to its period value, the ON bit will trigger, outputting a HIGH pulse until the timer is reset by an exterior reset source, such as Timer 2 or in software.

*Important Note* The post-scaler will not work when the timer is in Monostable or One-Shot mode.


Change the Clock Source to LFINTOSC so that the two timers operate on the same time base and align properly. For this tutorial, we will produce a 25% duty cycle, so change the Prescaler to 1:128 and the Timer Period to 250 ms. Once you have completed all these items, it should look like this:


Make sure to not adjust the Post-scaler while in **Monostable or One-Shot mode, as this can cause issues with the timing**


Under Device Resources you will find the CLC peripheral. Click on the CLC drop down menu and choose a CLC from the list. This should open the CLC Module in the central window, giving you a range of configuration options. Change the Mode to SR-Latch. It should now look like the figure below:


Now that we have each of the individual peripherals set up, it is time to use the CLC to connect everything together. Timer 2 will connect to the SET on the SR-Latch while Timer 4 is connected to RESET. Timer 2 sends a one clock cycle long pulse every 1 s which sets Q, or the output of the SR-Latch, HIGH. This simultaneously triggers Timer 4 low for 250 ms. Afterwards, Timer 4 will output a HIGH and reset the output of the SR Latch to LOW until the next Timer 2 pulse which sets Q HIGH again, as well as resetting Timer 4 to LOW for another 250 ms. You can see this visually in the figure below:


In order to accomplish this, we need to connect Timer 2 to the SET of the SR Latch and the Timer 4 to the RESET. Reopen the CLC module and connect the timers as seen below:


TMR2 = PR2 and TMR4 = PR4 refers to the point at which the Timer 2 and Timer 4 counters reach their respective period register values. To connect each to the CLC, click once in the circled squares. Once you have finished setting up the CLC, the last thing to do will be to set-up the output pins.


In the Pin configurator at the bottom of the MCC window, click the lock that intersects Port A, Pin 5 column to the CLC1OUT row:


CLC1OUT can be connected to any of the blue locks in its row, and even multiple outputs at the same time if desirable. If you choose RA0 through RA4 you can also see the PWM value turning ON/OFF the on-board LEDs. However, I wanted to grab a clean signal for the Oscilloscope output to observe. Once you have finished this step, click the generate button:



If you return to the MPLAB Xpress Online IDE, you should now see that the Header and Source files of your program have been populated with the correct peripherals, which should include Timer 2, Timer 4, the CLC, etc.:



Re-compile and download the project .hex file by clicking on the Make and Program Device button at the top of the MPLAB Xpress IDE.




Here is an oscilloscope view of the signals we produced from the output of the CLC as well as Timer 4. I would also show the output of Timer 2, but because it is a signal clock pulse in length, it is too fast for the oscilloscope I am using to pick up the pulse:


The top signal is our CLC output signal. If you could see the pulse of Timer 2, it would pulse at the rising edge of the CLC output and the falling edge of the Timer 4 output. You can see from the diagram that those two edges are aligned. Next, once the 4 ms period of Timer 4 has passed, the output of Timer 4 goes HIGH. Simultaneously, the CLC Output goes LOW. You can see on the right side of the image that the pulse width and period values agree with what we set them to within a margin of error.


This tutorial is meant to help supplement a system where you may need an additional PWM, but your chip does not have any PWM or CCP modules left to use. The strength of the CLC is its ability to combine several different peripherals to create entirely new signals, without needing physical rewiring or adding costly extra components to the chip. Plus, this entire process is completed without needing to write a single line of code. This can decrease response time and increase memory used.

Using two timers and the CLC, we were able to create an entirely independent PWM that can be set and changed regardless of the other PWMs being used on the device. However, the CLC does not only create PWMs. The next section provides links to even more complicated signals that the CLC enables the creation of, or that can simply serve as a jumping off point for you to create a new peripheral not even mentioned here or below!

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