SAM L10/L11 AHB Matrix

Description

The multi-layer Bus Matrix increases the system bandwidth by enabling parallel access paths between multiple Advanced High Performance Bus (AHB) Masters and Slaves in the system.

Features

The high-speed Bus Matrix has the following features:

  • 32-bit data bus
  • Allows concurrent accesses from different Masters to different Slaves
  • Operation at a one-to-one clock frequency with the bus Masters
saml10-ahb-matrix.png

The AHB Matrix is composed of:

  • Three Multi-Slave Master ports:
    • Arm® Cortex® -M23 core
    • Design Service Unit (DSU)
    • Direct Memory Access Controller (DMAC) Data access
  • Seven Slave ports:
    • Embedded Flash Memory
    • AHB-APB Bridge A
    • AHB-APB Bridge B
    • AHB-APB Bridge C
    • Boot ROM
    • Three ports dedicated to the SRAM Controller:
      • SRAM Port 0 - Cortex-M23 Access
      • SRAM Port 1 - DMAC Access
      • SRAM Port 2 - DSU Access

The AHB Matrix offers privileged SRAM-access Masters which have direct access to some dedicated SRAM ports:

  • DMAC - Fetch 0 Access
  • DMAC - Fetch 1 Access
  • DMAC - Write Back 0 Access
  • DMAC - Write Back 1 Access

These privileged SRAM-access Masters rely on SRAM quality of service to define priority levels
(SRAM Port ID).

SRAM Quality of Service

To ensure that Masters with latency requirements get sufficient priority when accessing RAM, priority levels can be assigned to the Masters for different types of access. The Quality of Service (QoS) level is independently selected for each Master accessing the RAM. For any access to the RAM, the RAM also receives a QoS level.

saml10-ahb-matrix_sram_qos.png

Refer to the product data sheet for more details on the SRAM QoS.

Related Sections

 
Processor Core
Learn more >
 
Direct Memory Access
Learn more >
 
Device Service Unit
Learn more >
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