SAM L10/L11 Direct Memory Access Controller (DMAC)

Direct Memory Access Controller (DMAC)

Overview

The DMAC contains both a Direct Memory Access engine and a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention and frees up CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication modules.

The DMA part of the DMAC has several DMA channels, which all can receive different types of transfer triggers to generate transfer requests from the DMA channels to the arbiter (see the Block Diagram below). The arbiter will grant one DMA channel at a time to act as the active channel. When an active channel has been granted, the fetch engine of the DMAC will fetch a transfer descriptor from the SRAM and store it in the internal memory of the active channel, which will execute the data transmission. An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel. The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, and grant the higher prioritized channel to start the transfer as the new active channel. Once a DMA channel is done with its transfer, interrupts and events can be generated optionally.

The DMAC has four bus interfaces:

  • The data transfer bus is used for performing the actual DMA transfer.
  • The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC.
  • The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data transfer can be started or continued.
  • The write-back bus is used to write the transfer descriptor back to SRAM.

All buses are AHB master interfaces but the AHB/APB Bridge bus, which is an APB slave interface. The CRC engine can be used by software to detect an accidental error in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the incorrect data.

Features

  • Data transfer from:
    • Peripheral-to-peripheral
    • Peripheral-to-memory
    • Memory-to-peripheral
    • Memory-to-memory
  • Transfer trigger sources
    • Software
    • Events from Event System
    • Dedicated requests from peripherals
  • SRAM based transfer descriptors
    • Single transfer using one descriptor
    • Multi-buffer or circular buffer modes by linking multiple descriptors
  • Up to eight channels
    • Enable eight independent transfers
    • Automatic descriptor fetch for each channel
    • Suspend/resume operation support for each channel
  • Flexible arbitration scheme
    • Four configurable priority levels for each channel
    • Fixed or round-robin priority scheme within each priority level
  • From 1 to 256 KB data transfer in a single block transfer
  • Multiple addressing modes
    • Static
    • Configurable increment scheme
  • Optional interrupt generation
    • On block transfer complete
    • On error detection
    • On channel suspend
  • Four event inputs
    • One event input for each of the four least significant DMA channels
    • Can be selected to trigger normal transfers, periodic transfers or conditional transfers
    • Can be selected to suspend or resume channel operation
  • Four event outputs
    • One output event for each of the 4 least significant DMA channels
    • Selectable generation on AHB, block, or transaction transfer complete
  • Error management supported by the write-back function
    • Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer
  • CRC polynomial software selectable to
    • CRC-16 (CRC-CCITT)
    • CRC-32 (IEEE® 802.3)

Block Diagram

saml10-dir-mem-access-controller.png

Code Example

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