SAM L10/L11 Real Time Counter (RTC)

Real-Time Counter (RTC)

Overview

The RTC is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously, in any sleep mode where the selected source clock is running, to keep track of time.

The RTC can wake up the device from Sleep modes using the alarm/compare wake up, periodic wake up, or overflow wake up mechanisms, or from the wake inputs. The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and peripheral event and can be reset on the occurrence of an alarm/compare match. This allows periodic interrupts and peripheral events at very long and accurate intervals.

The 10-bit programmable prescaler can scale down the clock source, enabling a wide range of resolutions and time-out periods to be configured. With a 32.768 kHz clock source, the minimum counter tick interval is 30.5 μs, and time-out periods can range up to 36 hours. For a counter tick interval of 1 s, the maximum time-out period is more than 136 years.

Features

  • 32-bit counter with 10-bit prescaler
  • Multiple clock sources
  • 32-bit or 16-bit counter mode
  • One 32-bit or two 16-bit compare values
  • Clock/Calendar mode
    • Time in seconds, minutes, and hours (12/24)
    • Date in day of the month, month, and year
    • Leap year correction
  • Digital prescaler correction/tuning for increased accuracy
  • Overflow, alarm/compare match and prescaler interrupts and events
    • Optional clear on alarm/compare match
  • Two general purpose registers
  • Tamper Detection
    • Timestamp on event or up to five inputs with debouncing
    • Active layer protection

Principle of Operation

The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Main Clock module (MCLK), and the default state of CLK_RTC_APB can be found in "Peripheral Clock Masking" section. A 32 kHz or 1 kHz oscillator clock (CLK_RTC_OSC) is required to clock the RTC. This clock must be configured and enabled in the 32KHz Oscillator Controller (OSC32KCTRL)* before using the RTC. This oscillator clock is asynchronous to the bus clock (CLK_RTC_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains.

The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends on the RTC operating mode.

The RTC can function in one of these modes:

  • Mode 0 - COUNT32: RTC serves as a 32-bit counter
  • Mode 1 - COUNT16: RTC serves as a 16-bit counter
  • Mode 2 - CLOCK: RTC serves as a clock/calendar with alarm functionality

Block Diagrams

MODE 0 – 32-Bit Counter

saml10-real-time-counter_mode0.png


When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x0, the counter operates in 32-bit Counter mode. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of 0xFFFFFFFF, and then wrap back to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format.

The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match occurs, the Compare 0 Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.CMP0) is set on the next 0-to-1 transition of CLK_RTC_CNT. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is '1', the counter is cleared on the next counter cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or events with longer periods than the prescaler events.

Note that when CTRLA.MATCHCLR is '1', INTFLAG.CMP0 and INTFLAG.OVF will both be set simultaneously on a compare match with COMP0.

MODE 1 – 16-Bit Counter

saml10-real-time-counter_mode1.png


When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x1, the counter operates in 16-bit Counter mode. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. While in 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value and then wrap back to 0x0000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format.

The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0..1). When a compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0..1) is set on the next 0-to-1 transition of CLK_RTC_CNT.

MODE 2 – Clock / Calendar

saml10-real-time-counter_mode2.png


When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x2, the counter operates in Clock/Calendar mode. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a 1 Hz clock to the counter for correct operation in this mode. The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format.

Time is represented as:

  • Seconds
  • Minutes
  • Hours

Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control A register (CTRLA.CLKREP). This bit can be changed only while the RTC is disabled.

The date is represented in this form:

  • Day as the numeric day of the month (starting at 1)
  • Month as the numeric month of the year (1 = January, 2 = February, etc.)
  • Year as a value from 0x00 to 0x3F. This value must be added to a user-defined reference year. The reference year must be a leap year (2016, 2020, etc).
    • For example, the year value 0x2D added to the reference year 2016, represents the year 2061.


The RTC will increment until it reaches the top value of 23:59:59 December 31 of year value 0x3F, and then wrap back to 00:00:00 January 1 of year value 0x00. This will set the Overflow Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.OVF).

The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs, the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARM0) is set on the next 0-to-1 transition of CLK_RTC_CNT (i.e., for a 1 Hz clock counter, it means the Alarm 0 Interrupt flag is set with a delay of 1 second after the occurrence of alarm match).

A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register (MASK0.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are ignored. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is set, the counter is cleared on the next counter cycle when an alarm match with ALARM0 occurs.
This allows the RTC to generate periodic interrupts or events with longer periods than it would be possible with the prescaler events only.

Note: When CTRLA.MATCHCLR is '1', INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match with ALARM0.

Refer to the "RTC – Real-Time Counter" chapter from the product data sheet to get more details.

Code Example

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