SAM L10/L11 SERCOM Inter-Integrated Circuit (I2C)

SERCOM Inter-Integrated Circuit (I2C)

Overview

The Inter-Integrated Circuit (I2C) interface is one of the available modes in the Serial Communication (SERCOM) interface. The I2C interface uses the SERCOM transmitter and receiver.

A SERCOM instance can be configured to be either an I2C Master or an I2C Slave. Both Master and Slave have an interface containing a shift register, a transmit buffer, and a receive buffer. In addition, the I2C Master uses the SERCOM baud-rate generator, while the I2C Slave uses the SERCOM address match logic.

Features

SERCOM I2C includes the following features:

  • Master or Slave operation
  • Can be used with DMA
  • Philips I2C compatible
  • SMBus™ compatible
  • PMBus compatible
  • The SERCOM peripheral supports several I2C bidirectional modes:
    • Standard mode (Sm) up to 100 kHz
    • Fast mode (Fm) up to 400 kHz
    • Fast mode Plus (Fm+) up to 1 MHz
    • High-speed mode (Hs) up to 3.4 MHz
  • 4-Wire operation supported
  • Physical interface includes:
    • Slew-rate limited outputs
    • Filtered inputs
  • Slave operation:
    • Operation in all sleep modes
    • Wake up on address match
    • 7-bit and 10-bit address match in hardware for:
      • Unique address and/or 7-bit general call address
      • Address range
      • Two unique addresses can be used with DMA

Block Diagram

saml10-sercom-i2c.png

Principle of Operation

In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT). When the SERCOM is used in I2C mode, the SERCOM controls the direction and value of the I/O pins. Both PORT control bits, PINCFGn.PULLEN and PINCFGn.DRVSTR, are still effective. If the receiver or transmitter is disabled, these pins can be used for other purposes.

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller (MCLK). Two generic clocks are used by SERCOM, GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW. The core clock (GCLK_SERCOMx_CORE) can clock the I2C when working as a Master. The slow clock (GCLK_SERCOM_SLOW) is required only for certain functions, e.g., SMBus timing. These two clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the I2C. These generic clocks are asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain registers require synchronization between the clock domains.

The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral the DMAC must be configured first. The interrupt request line is connected to the interrupt controller. In order to use interrupt requests of this peripheral, the Nested Vector Interrupt Controller (NVIC) must be configured first.

The I2C interface uses two physical lines for communication:

  • Serial Data Line (SDA) for data transfer
  • Serial Clock Line (SCL) for the bus clock

A transaction starts with the I2C Master sending the start condition, followed by a 7-bit address and a direction bit (read or write to/from the Slave). The addressed I2C Slave will then acknowledge (ACK) the address, and data packet transactions can begin. Every 9-bit data packet consists of eight data bits followed by a one-bit reply indicating whether the data was acknowledged or not. If a data packet is Not Acknowledged (NACK), whether by the I2C Slave or Master, the I2C Master takes action by either terminating the transaction by sending the stop condition, or by sending a repeated start to transfer more data.

Refer to the "SERCOM I2C – SERCOM Inter-Integrated Circuit" chapter from the product data sheet for more details.

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