SAM L10/L11 Timer Counter (TC)

Timer Counter (TC)


There are up to three Timer Counter (TC) peripheral instances. Each TC consists of a counter, a prescaler, compare/capture channels, and control logic. The counter can be set to count events or clock pulses. The counter, together with the compare/capture channels, can be configured to timestamp input events or I/O pin edges, allowing for capturing of frequency and/or pulse width. A TC can also perform waveform generation, such as frequency generation and pulse-width modulation.


  • Selectable configuration
    • 8-, 16- or 32-bit TC operation, with compare/capture channels
  • Two compare/capture channels (CC) with:
    • Double buffered timer period setting (in 8-bit mode only)
    • Double buffered compare channel
  • Waveform generation
    • Frequency generation
    • Single-slope pulse-width modulation
  • Input capture
    • Event or I/O pin edge capture
    • Frequency capture
    • Pulse-width capture
    • Time-stamp capture
  • One input event
  • Interrupts/output events on:
    • Counter overflow/underflow
    • Compare match or capture
  • Internal prescaler
  • Direct Memory Access (DMA) support

Block Diagram


Each TC instance has up to two compare/capture channels (CC0 and CC1). The counter in the TC can either count events from the Event System, or clock ticks of the GCLK_TCx clock, which may be divided by the prescaler. The counter value is passed to the CCx where it can be either compared to user-defined values or captured. The CCx registers are using buffer registers (CCBUFx) for optimized timing. Each buffer register has a buffer valid (BUFV) flag that indicates when the buffer contains a new value.

The Counter register (COUNT) and the Compare and Capture registers with buffers (CCx and CCBUFx) can be configured as 8-, 16- or 32-bit registers, with according to max values. Mode settings (CTRLA.MODE) determine the maximum range of the Counter register. In 8-bit mode, a Period Value (PER) register and the Period Buffer Value (PERBUF) register are also available. The counter range and the operating frequency determine the maximum time resolution achievable with the TC peripheral.

The TC can be set to count up or down. Under normal operation, the counter value is continuously compared to the top or zero value to determine whether the counter has reached that value. On a comparison match, the TC can request DMA transactions or generate interrupts or events for the Event System. In compare operation, the counter value is continuously compared to the values in the CCx registers. In case of a match, the TC can request DMA transactions, or generate interrupts or events for the Event System.

In Waveform Generator mode, these comparisons are used to set the waveform period or pulse width. Capture operation can be enabled to perform input signal period and pulse width measurements, or to capture selectable edges from an I/O pin or internal event from Event System.

Principle of Operation

In order to use the I/O lines of this peripheral, the I/O pins must be configured using the IO Pin Controller (PORT).

The TC bus clocks (CLK_TCx_APB) can be enabled and disabled in the Main Clock Module. The default state of CLK_TCx_APB can be found in the Peripheral Clock Masking. The generic clocks (GCLK_TCx) are asynchronous to the user interface clock (CLK_TCx_APB). Due to this asynchronicity, accessing certain registers will require synchronization between the clock domains.

Two instances of the TC may share a peripheral clock channel. In this case, they cannot be set to different clock frequencies.

The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral, the DMAC must be configured first. The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first.

The following registers are enable-protected, meaning that they can only be written when the TC is disabled (CTRLA.ENABLE = 0):

  • Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits
  • Drive Control register (DRVCTRL)
  • Wave register (WAVE)
  • Event Control register (EVCTRL)

Writing to Enable-Protected bits and setting the CTRLA.ENABLE bit can be performed in a single 32-bit access of the CTRLA register. Writing to Enable-Protected bits and clearing the CTRLA.ENABLE bit cannot be performed in a single 32-bit access.

Before enabling the TC, the peripheral must be configured by the following steps:

  1. Enable the TC bus clock (CLK_TCx_APB).
  2. Select 8-, 16- or 32-bit counter mode via the TC Mode bit group in the Control A register (CTRLA.MODE). The default mode is 16-bit.
  3. Select one wave generation operation in the Waveform Generation Operation bit group in the WAVE register (WAVE.WAVEGEN).
  4. If desired, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
    • If the prescaler is used, select a prescaler synchronization operation via the prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC).
  5. If desired, select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT).
  6. If desired, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to the Counter Direction bit in the Control B register (CTRLBSET.DIR).
  7. For capture operation, enable the individual channels to capture in the Capture Channel x Enable bit group in the Control A register (CTRLA.CAPTEN).
  8. If desired, enable inversion of the waveform output or IO pin input signal for individual channels via the Invert Enable bit group in the Drive Control register (DRVCTRL.INVEN).

Refer to the "TC – Timer/Counter" chapter from the product data sheet for more details.

Code Example

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