SAM L11 Processor Overview

Cortex M23 Processor

The SAM L11 implements the ARM® Cortex®-M23 processor, based on the ARMv8-M Baseline Architecture, which is the smallest and most energy-efficient ARM processor with ARM TrustZone® security technology.

The implemented ARM Cortex-M23 is revision "r1p0".

The ARM Cortex-M23 core has two bus interfaces:

  • Single 32-bit AMBA®-5 AHB-Lite system interface that provides connections to peripherals and memories.
  • Single 32-bit I/O port bus interfacing to the PORT and Crypto Accelerator peripherals with 1-cycle load and store.


For more information, refer to the following documents available from ARM:

"White Paper: Cortex-M for Beginners - An overview of the ARM Cortex-M processor family and comparison"

The ARM Cortex-M family now has five processors. This paper compares the features of various Cortex-M processors and highlights considerations for selecting a suitable processor for your application. The paper includes detailed comparisons of the Cortex-M instruction sets and advanced interrupt capabilities, along with system-level features, debug and trace features, and performance comparisons.

"ARMv8-M Architecture Reference Manual"

This is the specification of the architecture on which the Cortex M23 is based. It covers detailed information about the programmer's model.

"ARM Cortex-M23 Devices Generic Users Guide"

Targeted for application software developers, it provides information on the programmer's model, details on using the core peripherals such as Nested Vectored Interrupt Controller (NVIC), and general information about the instruction set.

"ARM Cortex-M23 Technical Reference Manual"

Targeted for silicon designers, this document contains implementation-specific information, such as instruction timing, and some of the interface information.

Cortex-M23 Configuration

Table 1 shows the configurable options for the core and which options are enabled for the SAM L11 implementation:

Table 1

saml11-core-configuration.png

Cortex-M23 Core Peripherals

System Timer (SysTick)

The System Timer (SysTick) is a 24-bit timer that extends the functionality of both the processor and the NVIC. Refer to the "Cortex-M23 Devices Generic Users Guide" for details.

Nested Vectored Interrupt Controller (NVIC)

External interrupt signals connect to the NVIC and the NVIC prioritizes the interrupts. The software can set the priority of each interrupt. The NVIC and the Cortex-M23 processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. Refer to the "Cortex-M23 Technical Reference Manual" as well as the "Cortex-M23 Devices Generic Users Guide" for details.

Single-Cycle I/O Port Bus (IOBUS)

The Cortex-M23 processor implements a dedicated, Single-Cycle I/O Port Bus (IOBUS) for high-speed, single-cycle access to certain peripherals. The IOBUS is memory-mapped and supports all the load and store instructions. This bus is used on SAM L10 to provide single-cycle access to the PORT registers.

System Control Block (SCB)

The System Control Block (SCB) provides system implementation information and system control. This includes configuration, control, and reporting of the system exceptions. Refer to the "Cortex-M23 Technical Reference Manual" for details.

© 2019 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.