CLC: Configurable Logic Cell

The Configurable Logic Cell (CLC) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 16 input signals and through the use of configurable gates reduces the 16 inputs to four logic lines that drive one of eight selectable single-output logic functions.

Input sources are a combination of the following:

  • I/O pins
  • Internal clocks
  • Peripherals
  • Register bits

The output can be directed internally to peripherals and to an output pin.
Possible configurations include:

  • Combinatorial Logic
    • AND
    • NAND
    • AND-OR
    • OR-XOR
    • OR-XNOR
  • Latches
    • S-R
    • Clocked D with Set and Reset
    • TransparentDwithSetandReset
    • Clocked J-K with Reset

CLC Video Tutorial

This video introduces the Configurable Logic Cell (CLC) for Microchip 8-bit MCU devices and shows how to use it.

CLC Setup

The CLC peripheral has four sections that need to be setup before it can be used.
This involves setting up 8 registers in your software program.
Once these registers are setup, the CLC will run independent of software control until the registers are changed via software.

They include:

A PIC Device can have multiple CLC's so each CLC module has its own set of 8 registers. The x in the register names above represent the CLC number (i.e. CLC1 uses the CLC1CON register).

To simplify the setup, the CLC can be broken down into four sections that need to be configured.
They include:

  • Inputs
  • Data Gating
  • Logic Function
  • Output Setting


Inputs can come from 8 to 16 different sources, depending on the PIC device, and from this list up to four can be chosen to feed the data gating section.
They can include:

  • I/O pins
  • Internal Clock outputs
  • Peripherals outputs
  • Register Bits

The inputs are selected by bits in the CLCxSEL0 and CLCxSEL1 registers.


Each input has an associated 3-bit code that is placed in the CLCxSEL registers to enable the input.


Data Gating

The Data Gating section has four logic gates that need to be setup. This requires five separate registers to be setup. The configure the inverted or non-iverted connection from the inputs that control the CLC peripheral. The five registers include:

  • CLCxGLS0
  • CLCxGLS1
  • CLCxGLS2
  • CLCxGLS3

Each gate starts off as a base OR gate but each input and output can be individually inverted or not inverted.
This allows AND, NAND, OR and NOR gates to be created. The gates can also be setup to drive a constant 1 or 0 logic level.


Each input to a data gate has a pair of bits in one of the CLCxGLSx registers. The two bits include a non inverted (T) bit and an inverted (N) bit that need to be setup. If the T bit is set then the input is non-inverted. If the N bit is set then the input is inverted. If both are set to zero then the input is not connected to the gate.


The CLCxPOL register bit LCxGxPOL bit will invert or non invert the output of the gate.
0 - non inverted
1 - inverted

Logic Function

The Logic Function has eight options to choose from. It is selected in the CLCxCON register.
Each Logic Function has a 3-bit code associated with it.


The 3-bit code is set in the CLCxCON register LCxMODE bits to enable the selected Logic Function.



All of the CLC sections reduce down to a single output that can drive an I/O pin, feed another CLC module or internal peripheral or can also trigger an rising or falling edge interrupt.
These various options are setup in the CLCxCON and CLCxPOL registers.


The bits in the CLCxCON register control the output settings.

LCxEN – CLC module enable bit (1 - CLC On, 0 - Off )
LCxOE – Output enable bit (1 – Enable, 0 – Disable)
LCxOUT - Internally monitor output via software (Read Only Bit)
LCxINTP – Rising Edge interrupt enable (1-CLCxIF set on Rising Edge)
LCxINTN – Falling Edge interrupt enable (1-CLCxIF set on Falling Edge)


CLC Example

Here is a simple example that shows the eight registers setup in software to create the CLC setup shown in the picture.


CLC Designer Tool

The CLC Designer Tool is a GUI based tool that you can download for free to make creating the CLC structure much easier. Through a series of setup options the tool will automatically output the eight register settings in C or Assembly language code format so you can include it in your MPLAB X project. The CLC Designer Tool is part of the MPLAB MCC Software tool

© 2019 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.