Hardware Limit Timer - Interrupts

The Hardware Limit Timer (HLT) can generate an optional device interrupt. The Hardware Limit Timer (HLTMRx) register output signal provides the input for the 4-bit postscaler. The overflow output of the postscaler sets the HLTMRxIF bit of the Peripheral Interrupt Register (PIR1).

The interrupt is enabled by setting the HLTMRx Match Interrupt Enable (HLTMRxIE) bit of the Peripheral Interrupt Enable (PIE1) register.

Only devices that have the HLT peripheral will have the Interrupt Enable bits. For more information on 8-Bit PIC® MCU Interrupts visit the interrupts page.

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