The Timer1 module is a 16-bit timer/counter within most PIC® MCU devices. Timer1 can increment up to a value of 65535 before it overflows back to zero. Because the timer is built into an 8-bit device, the 16-bit timer register is broken into two 8-bit registers and increments similar to an 8-bit timer with 8-bit prescaler. Timer1 has other built-in features that make it very useful for applications.

Timer1 has the following features:

  • 16-bit timer/counter register pair (TMR1H:TMR1L)
  • Programmable internal or external clock source
  • Prescaler
  • Dedicated 32 kHz oscillator drive circuit
  • Multiple Timer1 gate (count enable) sources
  • Interrupt on overflow
  • Wake-up on overflow (external clock, Asynchronous mode only)
  • External Gate Control for Signal Time Capture

Timer1 is also used as the time base for the Capture/Compare function.


Timer1 Operation

The Timer1 16-bit incrementing counter is accessed through the TMR1H:TMR1L register pair. To preload the timer, these registers can be updated directly with writes to the TMR1H or TMR1L registers. Timer1 is incremented by either the system clock, instruction clock, or an external clock signal. When used with a system or instruction clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.

Timer1 must be enabled to operate. This is done by setting the Timer1 On (TMR1ON) bit in the Timer1 Control (T1CON) register. This starts incrementing the counter on each pulse from the selected clock source.


Timer1 Clock Source

The Timer1 Clock Source is the input signal that increments the Timer1 counter. The clock source is selected by the Timer1 Clock Select (TMR1CS<1:0>) bits in the T1CON register.


There are four clock selections which include:


Note: On older devices, there are only three clock source options as the fourth optional selection is not included. On those devices, the TMR1CS is a single bit in the T1CON register.

Fosc/4 Instruction Clock Source (00)

When the instruction clock (Fosc/4) is selected (TMR1CS <1:0> = 00), Timer1 is incremented by the system oscillator through a divide by four scalers (Fosc/4). The TMR1H:TMR1L register pair will be incremented on the rising edge of the instruction clock. Any reads of the TMR1H:TMR1L registers are done based on this Fosc/4 instruction clock.

Fosc System Clock Source (01)

The Fosc is the system oscillator. When the Fosc system clock is selected (TMR1CS <1:0> = 01) as the Timer1 Clock Source, Timer1 is incremented by the system oscillator clock directly. The TMR1H:TMR1L register pair will be incremented on the rising edge of the oscillator clock. One thing to recognize is that any reads of the TMR1H:TMR1L registers are done based on the instruction clock (Fosc/4), even when the Fosc is selected as the Timer1 clock. When the Fosc internal clock source is selected, the Timer1 register value will increment by four counts for every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value.

External Clock Source (10)

When the external clock is selected (TMR1CS<1:0> = 10*), the Timer1 Oscillator Enable (T1OSCEN) bit selects the external signal source. The Timer1 module may work as a counter using an I/O pin as the input source, or a timer using an external 32 kHz clock oscillator.


When a counter is desired, the T1CKI input is selected by the Timer1 Oscillator Enable (T1OSCEN) bit. Timer1 is incremented on the rising edge of the external clock input signal at the T1CKI pin, which can be synchronized to the microcontroller system clock or can run asynchronously.

External 32 kHz Clock Oscillator

When a timer with a separate clock oscillator is desired, the T1OSCEN bit is set to the crystal oscillator mode. When this mode is selected, the Timer1 structure will also enable a dedicated low-power 32.768 kHz oscillator drive circuit built internally between I/O pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz "clock crystal". This can enable Timer1 to act as a dedicated real-time clock. The oscillator will continue to run during Sleep. More details on this option can be found at: Timer1 Secondary Oscillator.


Timer1 Asynchronous Mode

When the External Clock mode is selected as the Timer1 source, it can run asynchronously to the system clock. The Timer1 External Clock Input Synchronization Control bit (T1SYNC) of the T1CON register can be set to make the external clock un-synchronized. The timer will then increment asynchronously to the internal phase clocks. Running asynchronously allows the external clock source to continue incrementing the timer during Sleep and can generate an interrupt on overflow. The interrupt will wake up the processor so an internal time-based application can be updated. However, special precautions in software are needed to read/write the timer.


Reading and Writing to Timer1 in Asynchronous Counter Mode

Reading the TMR1H or TMR1L registers while Timer1 is running from an external asynchronous clock will return a valid read value as it is taken care of in hardware. For writes, it is recommended that you simply stop the timer and write the desired values for accurate implementation.

Optional Fourth Clock (11)

Low-Frequency Internal Oscillator

On some devices, Timer1 can be incremented separately by the Low-Frequency Internal Oscillator. This will allow Timer1 to increment independently of the system or instruction clock.

Capacitive Sensing Oscillator

On some devices, the capacitive sensing oscillator, which consists of a constant current source and a constant current sink to produce a triangle waveform, can be used as the oscillator designed to drive a capacitive load (single PCB pad). This clock source can also be shared to be the clock source to Timer1.

Timer1 Prescaler

Timer1 also has a prescaler that offers four options which allow 1:1, 1:2, 1:4, or 1:8 divisions of the clock input. The Timer1 Clock Prescaler (T1CKPS) bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable. However, the prescaler counter is cleared upon a write to TMR1H or TMR1L.


Timer1 Gate

The Timer1 Gate feature allows the PIC® MCU device to easily time external events using T1G pin as the input or analog events using an internal Comparator. This can be useful for timing the high pulse time of a waveform. The Timer1 Gate can control when the Timer1 increments. It is essentially an on/off switch for the Timer1 counter. There are several individual bits in the Timer1 Gate Control register (T1GCON register) that control the operation of the Timer1 Gate. Each setting is covered below.


Timer1 Gate Enable

The Timer1 Gate is enabled by setting the Timer1 Gate Enable bit (TMR1GE bit) of the T1GCON register. This enables control of the Timer1 count from an external source such as the T1G I/O pin or several other sources.

Timer1 Gate Value Status

The Timer1 Gate Value Status bit (T1GVAL bit) indicates when the Timer1 is active by being set high or at 1. When the gate control halts the operation, the T1GVAL bit will clear.

Timer1 Gate Polarity

The polarity of the Timer1 Gate is configured using the Timer1 Gate Polarity bit (T1GPOL bit) of the T1GCON. Setting this bit high will enable counting when the T1G pin is also high. Setting this bit low will enable counting when the T1G pin is low.

Timer1 Gate Source Selection

There are several source selections beyond the T1G i/O pin for controlling the Timer1 Gate, depending on the PIC MCU device being used. The options may include:

  • 11 - Comparator 2 Output
  • 10 - Comparator 1 Output
  • 01 - Timer0 Overflow
  • 00 - T1G I/O Pin

The two bits preceding the selections above are the two Timer1 Gate Source Select bits (T1GSS bits) of the T1CON register that select the control option.

Both Comparator outputs can start or stop the count based on the output signal level as it compares to the Timer1 Gate polarity setting. When the output matches the polarity setting, the count will increment on its clock source signal. When the output is opposite the polarity setting, then the count is halted.

The Timer0 overflow will send a high signal to the Timer1 Gate circuitry when it overflows from FFh to 00h. The Timer1 Gate Polarity setting will determine if the Timer1 starts to count (T1GPOL = 1) on the overflow signal or stops (T1GPOL = 0) on the overflow signal.

The T1G pin is a direct source for Timer1 gate control. It can be used to supply an external signal to control the operation.


Timer1 Gate Toggle Mode

The Timer1 Gate also has the option of a Toggle mode. It is enabled by setting the Timer1 Gate Toggle Mode bit (T1GTM bit) of the T1GCON register. The Toggle mode allows the Timer1 control to be based on alternating control signals.

When the signal matches the polarity setting, the Timer1 will start incrementing. When the control signal toggles to the opposite polarity, the Timer1 will be allowed to continue incrementing until the control signal matches the polarity a second time. At that point, it will stop incrementing and hold the value. This allows the Timer1 to measure the period of an alternating signal.


Timer1 Gate Single-Pulse Mode

Timer1 Gate Single-Pulse mode enables the time capture of a single-pulse event. This mode is first enabled by setting the Timer1 Gate Single Pulse Mode bit (T1GSPM bit) in the T1GCON register. Next, the Timer1 Gate Go/Done bit (T1GGO/DONE bit) in the T1GCON register must be set to 1. The Timer1 will begin counting on the next incrementing edge of the Timer1 Gate Source signal, beginning the measurement of a pulse.

On the following trailing edge of the pulse that is being measured, the T1GGO/DONE bit will automatically be cleared and the Timer1 count will be halted. The TMR1 register will contain the pulse width time measurement in timer counts. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software so the application can retrieve the value from the TMR1 register.

If the Single-Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.


Timer1 Gate Single-Pulse and Toggle Mode Together

Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows a full cycle to be captured and then the Timer1 halted with the total period time of the waveform.


Timer1 Gate Event Interrupt

An interrupt can be generated by the Timer1 Gate structure. The interrupt is based on the T1GVAL bit in the T1GCON register. When the falling edge of T1GVAL occurs, the Timer1 Gate Interrupt Flag bit (TMR1GIF flag bit) in the Peripheral Interrupt Register 1 (PIR1) will be set. If the Timer1 Gate Interrupt Enable bit (TMR1GIE bit) in the Peripheral Interrupt Enable Register 1 (PIE1) is set, enabling the interrupt, then an interrupt will be recognized and a redirect to the interrupt service routine will occur.

PIR1 Register


The TMR1GIF flag bit can be polled without enabling the Timer1 Gate interrupt, as the TMR1GIF flag bit operates even when the Timer1 gate interrupt is not enabled.

Timer1 Interrupt

Timer1 can trigger an interrupt when it overflows from FFFFh to 0000h. When Timer1 rolls over, the Timer1 Interrupt Flag (TMR1IF) bit of the Peripheral Interrupt 1 Register (PIR1) is set. Timer1 overflow can be monitored by randomly checking the TMR1IF bit.

An automatic interrupt can be enabled to redirect operation to the Interrupt Service Routine (ISR) as soon as Timer1 overflows. To enable the automatic interrupt on rollover, you must set these bits:

  • TMR1ON bit of the T1CON register
  • TMR1IE bit of the PIE1 register
  • PEIE bit of the INTCON register
  • GIE bit of the INTCON register

Note: For more information on the interrupt structure for 8-Bit devices, refer to the Enhanced Mid-Range Interrrupts training module.

The interrupt is cleared by clearing the TMR1IF bit in the ISR.

Timer1 Operation During Sleep

Timer1 can only operate during Sleep when set up in Asynchronous mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device:

  • Set the TMR1ON bit of the T1CON register
  • Set the TMR1IE bit of the PIE1 register
  • Set the PEIE bit of the INTCON register
  • Set the T1SYNC bit of the T1CON register
  • Configure the TMR1CS bits of the T1CON register
  • Configure the T1OSCEN bit of the T1CON register

The device will wake-up on a Timer1 overflow and execute the instructions following the SLEEP assembly command.

The wake up from Sleep can also drive the device to execute the Interrupt Service Routine instead of the instruction following the sleep command. To enable this, the Global Interrupt Enable (GIE) bit of the INTCON register needs to be set. The device will call the Interrupt Service Routine on wake-up. If the interrupt service routine contains a SLEEP instruction, the device will return to sleep mode. The service routine must also clear the TMR1IF prior to returning to Sleep.

© 2019 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.