DCDT Default Values

The Digital Compensator Design Tool (DCDT) Graphical User Interface (GUI) defines specific default values for many of your entry-fields. These are to be used as a starting point or reference, based on a typical application, but you are encouraged to measure and determine the actual values based on the hardware configuration settings. The section below gives a quick overview of the default values and how these were selected.

  • Pulse Width Modulation (PWM) Switching Frequency: 300 kHz is the default value used in all the different available compensators. This is a commonly used switching frequency in DC to DC converters.
  • PWM Sampling Ratio: The DCDT default sampling ratio is one (1), configuring the sampling frequency equal to the switching frequency. Particular attention should be paid that the sampling frequency used allows the microcontroller enough time to execute the control algorithm and any additional tasks the microcontroller is required to do (e.g., communication, fault monitoring, etc).
  • PWM Maximum Resolution: The DCDT by default configures the PWM hardware for the maximum resolution for dsPIC33F devices of 1.06 ns. Depending on the hardware requirement, you should adjust this value.
  • Computational Delay: The default compensator computational delays defined in the DCDT were determined based on hardware measurements on a dsPIC33 device operating at 40 MHz CPU clock speed. These are to be used as examples and you are encouraged to make time delay measurements in the specific hardware used.

Table 2 - Compensator Default Delay

Compensatpr Type Typical Compensator Delay (CPU at 50 MHz)
PID 1.1 us
2P2Z (Type II) 1.35 us
3P3Z (Type III) 1.5 us

The System Delays with 3-Pole/ 3-Zero (3P3Z) Compensator figure shown below is an example of a voltage mode converter, where the sampling frequency equals to the PWM switching frequency (Sampling Ratio = 1). This means that the Analog-to-Digital Converter (ADC) module will make a measurement of the output voltage once per PWM cycle. After the ADC has completed the conversion of the measurement, the ADC Interrupt Service Routine (ISR) will be called, inside of which the function call to the 3P3Z compensator will be executed and the new duty cycle will be written to the target PWM register.

System-Delays-with-3P3Z-Compensator.PNG
  • Gate Drive Delay: This is the delay associated with the gate-driver and the power switch (e.g., Metal–Oxide–Semiconductor Field-Effect Transistor, or MOSFET) delays. These delays are often very small but should be taken into account when calculating overall system performance. For simplicity purposes, this delay was not shown in the figure above. It is possible to measure it by using an oscilloscope at the output of the microcontroller PWM output to the time when the power switch (e.g., MOSFET drain terminal) is fully turned on.

For example:
Using Microchip MOSFET gate driver MCP14700, the datasheet specifies a Turn-On Propagation delay of 36 ns and the Turn-Off Propagation delay of 36 ns, rise and fall times of 10 ns for a total of 92 ns Gate Driver delays.

Using Microchip High-Speed N-Channel Power MOSFET MCP87050, defines a Turn-On Delay of 5 ns, a Rise time of 18 ns, Turn-Off delay of 11 ns and Fall-time of 5 ns, for a total of 39 ns. Additionally, combining the gate driver and the MOSFET delay equates to 131 ns.

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