Step 2.1: Configure Audio CODEC (AK4953)
1
Expand the Harmony Framework Configuration > Drivers > CODEC selection tree.
2
Check the Use Codec AK 4953? box.
3
A default value for Volume is specified. You can change the value depending on your requirements.
4
Do not check Specify MCLK value. A default value of 256 for the Master Clock (MCLK) is selected under the I²S driver configuration option MCLK Sampling Rate Multiplier.
5
Only one client of the CODEC driver needs to be opened, therefore retain the Number of AK4953 Driver Clients value to 1.
6
The AK4953 driver supports only one instance of the AK4953 CODEC module. The AK4953 driver is a single instance driver. Therefore the default instance of Codec AK4953 Driver Instance 0 is selected.
7
Select the I²S driver (used for data interface) instance as DRV_I2S_INDEX_0. The AK4953 driver uses the I²S interface for the audio data transfer to/from the PIC32 microcontroller. The PIC32MZ2048EFH144 device supports multiple instances of I²S modules. An instance (Instance 0) for audio data communication is selected.
8
Select the I²C driver (used for control interface) instance as DRV_I2C_INDEX_0 (or 0). The AK4953 driver uses the I²C interface for the audio control transfers to/from the PIC32 microcontroller. The control transfers exchange commands to/from the AK4953 CODEC to configure and/or read the initialized/existing configuration. The PIC32MZ2048EFH144 device supports multiple instances of I²C modules. An instance (Instance 0) for audio control communication is selected.
The CODEC devices need a fine clock source to generate accurate audio sampling rates. The clock source (MCLK from the CODEC device’s perspective) can be generated internally by the CODEC device.
PIC32 devices have a flexible reference clock output. The Reference Clock Output module (REFCLKO) can be used to generate the fractional clock that can be used by audio CODEC/DACs to accommodate various sample rates.
The MCLK value represents the multiplier to the sampling frequency (Left and Right Clock (LRCK)) which produces the value for the Master/Reference Clock (MCLK/REFCLOCK) to the CODEC. This value should be one of the fs values supported by the CODEC for various sampling rates.
For example: For 256 fs, The MCLK value of 256 for a sampling rate of 48000 Hz would generate an MCLK/REFCLOCK of 12288000 Hz. By default, an MCLK value of 256 is selected. This is also shown in the default I²S driver configuration options MCLK Sampling Rate Multiplier. If you intend to select a different MCLK value, check Specify MCLK value. Selectable options include: 128, 192, 256, 384, 512, 768, and 1152.
Step 2.2: Configure I²C driver for CODEC
In AK4953 CODEC driver configurations, I²C is selected as the control interface medium (expand Harmony Framework Configuration > Drivers > CODEC > Use Codec AK4953? selection tree to see this). Next, configure the I²C interface driver.
1
Expand the Harmony Framework Configuration > Drivers > I2C selection tree.
2
The Use I2C Driver? is checked by default. This is done since the AK4953 CODEC driver uses the I²C driver.
3
Select Dynamic for the Driver Implementation. A dynamic I²C driver implementation will allow the implementation to be used for another instance of the I²C module in this lab (needed for the touch screen).
4
Check the Interrupt mode option. This allows I²C data completion events to be detected asynchronously, without the need for polling for the transfer to complete. This is necessary because, by the end of the lab, you will add a number of Harmony drivers, system services, and middleware libraries. All these Harmony modules have to cooperatively run without blocking the processor.
5
Keep the Number of I2C Driver Clients and Number of I2C Driver Instances set to 1 since at this time the I²C is only used to interface with the AK4953 CODEC. You will increase this number in the following lab to enable this driver to support multiple I²C interfaces.
6
Check Include Force Write I2C Function. This will include an Application Programming Interface (API) that sends data to the Slave even if the Slave NACKs data. This is needed by the AK4953 CODEC since it NACKs I²C data during the initialization sequence.
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Under I²C Driver Instance 0, keep Use Bit Bang I2C Implementation? unchecked. Since the hardware I²C instance is used, use the driver for the real hardware instead of a bit banged driver implementation.
8
Select I2C_ID_2 as I²C Module ID. I²C module instance 2 is interfaced to the AK4953 CODEC’s control interface.
I2C_ID_2 refers to the PIC32 I²C peripheral (using pins SCL2 & SDA2). These pins are connected to the AK4953 audio CODEC on the MEB II board.
9
Retain default value DRV_I2C_MODE_MASTER for Operation Mode. PIC32 I²C module 2 will act as Master, and the AK4953 CODEC module control interface (I²C) will act as a Slave.
10
Retain default value for Master Interrupt Priority and Master Interrupt Sub-priority as INT_PRIORITY_LEVEL1 and INT_SUBPRIORITY_LEVEL0 respectively. The CODEC I²C events need to be signaled at a higher priority.
11
Retain default value for Error Interrupt Priority and Error Interrupt Sub-priority as INT_PRIORITY_LEVEL1 and INT_SUBPRIORITY_LEVEL0 respectively.
12
Baud Rate Generator Clock is configured to 99 MHz; this is derived from the Peripheral bus 2 clock frequency generated from 198 MHz system clock.
13
Retain default value of 50 KHz for I²C CLOCK FREQUENCY. The AK4953 CODEC supports fast I²C control interface (up to 400 kHz).
14
Retain Slew Rate Control as unchecked. This function enables the I²C module to use high-frequency signaling, allowing it to use the 400 kHz and 1 MHz signaling rates.
15
Retain default value of SYS_MODULE_POWER_RUN_FULL for Power State. Run the I²C module in Normal Power mode.
Step 2.3: Verify the I/O Pins Used by I²C Module
Select the MPLAB® Harmony Configurator tab and Pin Diagram sub-tab. In the lower window of MPLAB Harmony Configurator (MHC) select the Pin Table tab.
The I2C2 peripheral has dedicated pins for SCL2 and SDA2 signals. These pins are hardcoded and configured by the I²C driver.
Step 2.4: Configure I²S driver for CODEC
1
In AK4953 CODEC driver configurations, I²S is selected as the audio data interface medium. Next, configure the I²S interface driver.
Expand the Harmony Framework Configuration > Drivers > I2S selection tree.
2
The Use I2S Driver? is checked by default. This is done since the AK4953 CODEC driver uses the I²S driver.
3
Expand the Use I2S Driver? option.
4
Dynamic for Driver Implementation is selected by default and greyed out. The I²S driver does not support static implementation yet.
5
Check the box beside DMA Mode. Under Direct Memory Access (DMA) Mode, make sure the Transmit DMA Support and Enable DMA Channel Interrupts? boxes are checked. Transmit DMA Support is enabled to use DMA channels to transfer audio data from memory to I²S buffers. DMA Channel is interrupt enabled to allow DMA transfer completion notification.
6
Retain Stop in Idle Mode as it is.
7
Retain default Sampling Rate as 48000. This is the initial value of the sampling rate.
8
Retain default value of 256 for MCLK Sampling Rate Multiplier. The AK4953 CODEC supports 256 fs with 48000 Hz sampling rate for generating the REFCLOCK.
9
Retain default value of 4 for the Master Clock/Bit Clock ratio.
For a sampling rate of 48000 Hz and MCLK Sampling Rate multiplier value of 256, the MCLK or REFCLOCK = 256 * 48000 = 12,288,000 Hz. The common Bit Clock (BCLK) that can be generated for the given combination of MCLK and sampling rate would be REFCLOCK/1, REFCLOCK/2, REFCLOCK/4, or REFCLOCK/8.
For example, AK4953 CODEC supports BCLK value as either 32 fs or 64 fs. For the 48000 Hz sampling rate, the BCLK would be 64 * 48000 = 3072000 Hz. Therefore the MCLK/BCLK ratio is 12288000/3072000 = 4.
10
Retain default value of 1 set for the Number of I²S Driver Clients and Number of I²S Driver Instances. The I²S interface is used only for audio playback, therefore one instance of I²S driver and its client is sufficient.
11
Under I²S Driver Instance 0, retain SPI_ID_1 as I2S Module ID. The PIC32's Serial Peripheral Interface (SPI)/I²S1 peripheral (PIC32 pins: SCK1, SDI1, SDO1, and /SS1) is interfaced to the AK4953 CODEC’s data lines.
12
Retain default value of Usage Mode as DRV_I2S_MODE_MASTER. It indicates whether the I²S instance will act as a Master or Slave. In Master mode, PIC32 generates the BCLK to the Slave. In Slave mode, PIC32 receives BCLK from the I²S Master. In the interface to AK4953 CODEC, PIC32 I²S will act as a Master and hence generates the BCLK.
13
Retain default value of the Baud Clock as SPI_BAUD_RATE_MCLK_CLOCK. Indicates that the system clock of 198 MHz is used to generate the Baud rate.
14
Retain default value of Clock Mode as
DRV_I2S_CLOCK_MODE_IDLE_HIGH_EDGE_FALL. The default polarity for I²S protocol.
15
Change Audio Communication Width to SPI_AUDIO_COMMUNICATION_16DATA_16FIFO_32CHANNEL. In the scope of this lab, CD quality audio playback is supported, therefore setting 16-bit audio data per channel, 32-bit channel width.
16
Retain default value of Audio Mode as SPI_AUDIO_TRANSMIT_STEREO. The lab supports stereo audio Playback.
17
DRV_I2S_MODE_MASTER indicates whether the I²S instance will act as a Master or Slave. In Master mode, PIC32 generates the BCLK to the Slave. In Slave mode, PIC32 receives BCLK from the I²S Master. In the interface to AK4953 CODEC, PIC32 I²S will act as a Master and hence generates the BCLK.
18
Retain default value of Input Sample Phase Selection as SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE. The default phase for I²S protocol.
19
Retain default value of Audio Protocol Mode as DRV_I2S_AUDIO_I2S. I²S protocol interface mode is chosen as it is supported by AK4953 CODEC.
20
Retain Queue Size Transmit to 3. This will allow queuing of up to three audio buffer objects at a time.
21
Set Queue Size Receive to 1. Receive path is not utilized and hence a minimal value of one buffer object is set.
22
Retain Transmit DMA Channel Instance to 0. DMA Channel Instance 0 is used for audio data transfer.
23
Retain default value of SYS_MODULE_POWER_RUN_FUL for Power State. You want to run the I²S module in Normal Power mode.
Step 2.5: Configure CODEC Input Clock
1
The PIC32 acts as I²S Master to the AK4953 CODEC. It needs to give the REFCLOCK or External Master Clock Input (MCKI) to the CODEC in addition to the BCLK.
2
Expand the Harmony Framework Configuration > Options > System Services > Clock selection tree.
3
Expand Use Clock System Service?
4
Click Execute on Launch Clock Configurator
5
Locate the REFCLOK block. By default the Reference Clock #1 tab is selected. The Reference Clock #1 enables configuring the REFCLOK to SPI/I²S, PPS.
6
Check the ON box. This enables the reference clock circuitry.
7
Select SPLL as ROSEL1. The System Phase Locked Loop (PLL) is used as the source clock for generating the REFCLOK.
8
Click the Auto-Calculate button to generate the Reference Clock #1. It opens up windows Reference Clock Divisor and Trim Auto Calculator
9
Verify that the Reference Clock Divisor and Trim Auto Calculator show the desired REFCLOK and Sampling values to be generated. The values are generated from the MCLK multiplier and sampling rate specified in CODEC/I²S driver configuration.
10
Select the radio button Target I2S Input Frequency and click the Apply button. The Target I²S Input Frequency is the REFCLOK input to the AK4953 CODEC.
If the Target I²S Input Frequency is shown as 0, some I²S configuration is not properly done. Deselect and re-configure the I²S driver as explained above and come back to this step.
11
Click on the OE button to enable the Reference Clock #1 output.
It is important to note that a REFCLOK of 12288000 Hz cannot be accurately generated from a system clock of 200 MHz. It is for this reason that the system clock is configured to 198 MHz, during the oscillator settings step.
Step 2.6: Configure the DMA System Service for Audio
1
The I²S driver has been configured to use a DMA channel for transferring audio data to the CODEC.
2
Expand the Harmony Framework Configuration > Options > System Services > DMA selection tree.
3
Expand Use DMA System Service?
4
Retain Select Service Mode as Dynamic. This enables the same driver instance to manage multiple DMA channels (if required).
5
Keep the Number of DMA Channel Instances at 1. One DMA channel instance is used by I²S.
6
Expand the DMA Channel Instance 0. This is the instance set by the I²S driver for transferring audio data.
7
Under DMA Channel, select DMA_CHANNEL_2. DMA Channel 2 will be used for the I²S data transfer.
8
Retain Interrupt Priority and Interrupt Sub-Priority as INT_PRIORITY_LEVEL1 and INT_SUBPRIORITY_LEVEL0 respectively. I²S data transfer (DMA Completion) events are needed to be signaled at a higher priority.
Step 2.7: Verify/Set the I/O Pins Used by I²S Module
Select the MPLAB Harmony Configurator tab and Pin Diagram sub-tab. In the lower window of MHC select the Pin Table tab
1
Map the PIC32's Reference Clock Generator Output 1 signal (REFCLKO1) to pin 70 (RPD15). Click on the blue box to map this signal to this pin. This will change the color of the box from blue (available) to green (locked).
See the board schematics in the User's Guides for reference:
2
I2S1 has a dedicated pin for the SCK1 signal. This pin is hardcoded and configured by the I²S driver.
3
Map I2S1 signals SDI1, SDO1, and SS1(out) to pins RPD14, RPB10, and RPF12.
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