Digital Control Loop Designer Software Development Kit

The Digital Control Loop Designer is a Software Development Kit (SDK) consisting of one basic, main module combining multiple, individual stand-alone tools covering system definition, system modeling, code generation, control system fine-tuning, and real-time debugging of fully digital control systems for Switched-Mode Power Supplies (SMPS) supporting the dsPIC® Digital Signal Controllers (DSC).

The major scope of this tool is the rapid design of a digital power supply control stage rather than the power supply itself. This allows simplifying the design process to models based on interconnected transfer functions. These transfer functions are defined and configured in individual configuration windows. A transfer function can be based on generic Laplace-domain functions being calculated at runtime or on external data coming from network analyzer measurements or other third-party simulation tools such as MATLAB®, SciLab®, Simplis, LTSpice®, etc.

DCLD-model.png
Figure 1: Digital Control Loop Designer Software Development Kit

This software is still in a preliminary state with limited support. All features and functions are subject to change at any time without further notice. Please refer to the most recent readme.txt file to get updates on features and functions and to review the release history.

z-Domain Feedback Loop Configuration Module

In the current version, the essential functions of the z-domain configuration block of the Digital Control Library SDK enable the graphical design of z-Domain compensation filters from the first to the sixth order (1P1Z to 6P6Z). It also enables the generation of customized/tailored digital SMPS controller code libraries with standardized API, thereby removing the need to manually write DSP-specific source code. Additionally, the functions allow the display of analysis results on timing, number accuracy, and resolution.

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Figure 2: Controller Selection and s-Domain/z-Domain Loop Configuration
DCLD-block-diagram.jpg
Figure 3: Block Diagram Overview
DCLD-timing-diagram.jpg
Figure 4: Controller Execution Timing Analysis
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Figure 5: Code Generator Output

The standardized API of the generated controller library ensures seamless integration into the final firmware, supporting multiple, co-existing controllers in one firmware, and allows seamless migration between different controller types and scaling methods. This helps to solve the typical performance vs. accuracy and feature trade-offs without disruptive code changes in the user firmware.

For simplified use during code development, the z-Domain configuration window and code generator can be called directly from the MPLAB® X environment to make changes. For more details about this software and its features, please refer to the most recent user guide included in the download package of this software.

Known Limitations of this version:

  • Supported controllers
    • 1P1Z, 2P2Z, 3P3Z, 4P4Z, 5P5P, 6P6Z
  • Fixed-Point Number Scaling
    • Single-bit shift scaler, Dual bit-shift scaler (one for A-, one for B-coefficients), Coefficient Scaling Factor
  • Floating Point Number Scaling
    • 16-bit wide Fast Floating Point Scaling format (ffloat Coefficients, Q15/uint16_t Integer input, output, and history format
    • Full Fast Floating Point (ffloat) support in preparation
  • Timing Optimization recently only supports mode '0' - Pulse-Width Modulation (PWM) Interrupt Trigger (Minimum CPU Load) which is a highly linear code execution (calculate A-term, read error, update error history, calculate B-term, anti-windup, write-back, trigger positioning, control history update)
  • The Fast Response mode (where the most recent error is read, the last Multiply And Accumulate (MAC) is calculated, fed into anti-windup and immediately written back - all necessary updates are done at the end of the control routine) is not supported. Although seemingly desirable, it comes with a couple of down-sides:
    • Histories are distorted
    • Total CPU workload is higher (no linear execution)

Generally, you can achieve equal or better results if the controller is optimized using the Timing view and then using a PWM trigger to position the control loop execution over Analog-Digital-Converter (ADC) conversion time.

Eventually, it is the option between handling the overhead at the beginning or at the end. Due to the lower total CPU load and more generic nature of the code, we recommend the linear execution with PWM interrupts and the addition of the alternative execution mode later.

Recommended Procedure:

  1. Open the GUI.
  2. Go to the Source Code tab on the right.
  3. Specify the target paths for every generated file (assembly, C-source, C-header, Library header).
  4. Choose a name Prefix for the controller on the Source Code tab on the left.
  5. Go to Controller tab on the left and select the Bode Plot tab on the right.
  6. Select your controller and adjust poles and zeros.
  7. Check the rounding error of the coefficients (A-coefficients are the most critical ones) => The coefficient table should not show warnings (yellow or red) on A-coefficients.
  8. Select the Source Code tab on the left and the Timing tab on the right.
  9. Choose your code options (context saving, anti-windup, etc.).
  10. Click Tools>Generate Code (ALT+G).
  11. Click Tools>Export Generated Files>Export Files (SHIFT+F5).
  12. Save the configuration by clicking File>Save/Save As (CTRL+S).

Special Features:

  • Data export using menu Tools>Copy To Clipboard.
  • The Transfer Function (Bode Plot Data) Export of s-Domain and z-Domain: Copies the bode plot data table into the clipboard as tab-separated text table with column headers. This data can directly be pasted into MS Excel. The data table is set to 1601 points by default ranging from 1 Hz to 1 MHz.
  • Coefficient Declaration: This is practically the content of the C-source file and therefore, pretty much obsolete. You can select the generated code from the C-Source window and copy it.
  • Coefficient Table: All coefficients are exported in a block covering floating point, scaled floating point, fixed point, hex, int, and binary number format and the rounding error. This is more for documentation than for any other reasonable use case.
  • Config File Location: Copies the file location of the op-code file for the assembly code generation. This is the script used to build the assembly library. Unfortunately, the C-code is not script-based yet. Any larger modification affecting names or data structure elements would result in necessary changes to the DCLD code, which is not feasible. In future versions beyond v1.0, both (assembly and C) will be fully script-based to enable anyone to add and modify supported controllers without changing the main program. Nevertheless, should you decide to tweak the assembly code (e.g. comments, etc.), you can do so by editing this file.

Further Information:

This software is currently hosted on Github. For more information, please visit the repository WIKI on Github.

Download:

To download the Digital Control Library SDK software, please visit the Latest Release site on Github.

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