Accessing the PTG Registers

Accessing PTG Registers

In addition to the registers needed to implement the queue, the Peripheral Trigger Generator (PTG) is controlled by twelve Special Function Registers (SFRs). Although initializing twelve SFRs may appear a daunting task, it is important to realize that not all of the SFRs may need to be initialized. The default settings for the PTG SFRs are non-intrusive. If an SFR controls a parameter not specifically used in a sequence, that SFR does not need to be initialized for the sequence to execute properly.

The PTG SFRs are divided into five categories:

Control and Status Registers

PTGCST Provides overall control and status reporting for the PTG, including Enable/Disable, Start/Stop, and Trigger output type (Toggle or Pulse). This is the only register that can be accessed while the PTG is enabled.
PTGCON Determines the values used for many of the PTG timing parameters such as the clock source, any prescalers on the clock, and the width of the output triggers when the triggers are in Pulse mode. This register also controls the value of the PTG's Watchdog timer which limits the time the PTG will wait for a trigger.

Limit Registers

PTGT0LIM Determines the limit value for PTG Timer 0. Used by PTGCTRL to delay or pause the sequence.
PTGT1LIM Determines the limit value for PTG Timer 1. Used by PTGCTRL to delay or pause the sequence.
PTGSDLIM Sets the number of PTG clock cycles allocated to each step command. Using this register can slow down the speed in which PTG step commands are executed. The use of this Delay timer can be enabled or disabled with the PTGCTRL command.
PTGC0LIM Used to specify the loop count for the PTGJMP0 command.
PTGC1LIM Used to specify the loop count for the PTGJMP1 command

Hold and Adjust Registers

PTGHOLD Used by the PTGCOPY command, this register holds the value to be moved into one of the Limit registers or into the PTG Literal register (PTGL0).
PTGADJ Used by the PTGADD command, this register holds a value to be added to one of the Limit registers or the PTG Literal register (PTGL0).

Literal and Broadcast Registers

PTGL0 Holds a value to be written into the ADC1 channel select register (AD1CHS0). Only used by the PTGCTRL command. AD1CHS0 can also be written with the PTGSTRB command.
PTGBTE When the application wishes to simultaneously broadcast triggers to more than one peripheral (PTGCTRL command with OPTION = 0b1111), this register contains the list of triggers to generate.

PTG Queue Registers

PTGQPTR Points to the current step command being executed. When the PTG is enabled, this register is set to the first entry in the step queue.

These registers are the queue in which the step commands are located.

To prevent unintentional modifications to PTG operations caused by spurious writes to the PTG SFRs, the PTG Status and Control Register (PTGCST) is the only register that can be written to while the PTG is enabled. To modify PTG SFRs, other than PTGCST, you must ensure that the PTG is disabled (i.e. verify PTGCST<15> = 0).

© 2020 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.